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Analog Devices Floating Point Chip-Set Test Card

IP.com Disclosure Number: IPCOM000034608D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Satz, PJ: AUTHOR

Abstract

A hardware facility is described for the functional test of the analog devices floating point chip set used in the IBM RT-PC. The Analog Devices Floating Point-Chip Set test card, shown in the figure provides the necessary logic to interface between the 8-bit IBM PC bus and the ADSP (Analog Devices Signal Processor) Floating-Point Chip set. The ADSP chip set consists of the ADSP 3221 Floating-Point Arithmetic Logic Unit, the ADSP 3210 Floating Point Multiplier, and the ADSP 1401 microcode sequencer. These chips are used on the AFPA (Advanced Floating-Point Accelerator) in the RT-PC. The card allows all data and control inputs to the ADSP chip set to be software controllable.

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Analog Devices Floating Point Chip-Set Test Card

A hardware facility is described for the functional test of the analog devices floating point chip set used in the IBM RT-PC. The Analog Devices Floating Point-Chip Set test card, shown in the figure provides the necessary logic to interface between the 8-bit IBM PC bus and the ADSP (Analog Devices Signal Processor) Floating-Point Chip set. The ADSP chip set consists of the ADSP 3221 Floating-Point Arithmetic Logic Unit, the ADSP 3210 Floating Point Multiplier, and the ADSP 1401 microcode sequencer. These chips are used on the AFPA (Advanced Floating-Point Accelerator) in the RT-PC. The card allows all data and control inputs to the ADSP chip set to be software controllable. When inserted in a PC or RT-PC and the PC is programmed to write data and control information to the test card, the card can perform operations supported by the ADSP chip set. Resultant data and status can then be read from the test card. This card is used to functionally test the 3221, 3210, and 1401 and can be used as a facility for performing floating-point calculations in a PC or RT. A block diagram of the test card is shown in the figure. All address, data, and control line inputs are buffered to provide electrical isolation between the PC bus and the test card. Data outputs from the test card are also buffered. Address and control inputs are decoded, and the decode outputs are used to provide control signals to the input control latches and the bidirectional data latches. After four bytes of input data are latched by the test card, this data along with control information also contained on card are clocked into the ADSP parts. The control information is completely writeable and should be initialized before writing the data inputs to the card. However, once the five bytes of control information are initialized, they do not have to be reinitialized for later data input operations unless a change is desired. On read operations the address decode logic and the device select logic clock data from the ADSP parts to the bidirectional data latches and to the PC bus. Common clocking between the ADSP parts, address decode and device select logic allow the test card to properly implement the timing requirements of the ADSP parts and the bidirectional data latches. Test card logic external to the ADSP parts and ADSP part timing requirements will be met over a range of oscillator frequencies from 10 to 25 MHz. The test card oscil...