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Staggered High-Speed BICMOS Logic

IP.com Disclosure Number: IPCOM000034644D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Ludwig, T: AUTHOR [+4]

Abstract

The proposed scheme offers a very high BICMOS (BIpolar/Complementary Metal Oxide Silicon) circuit performance by staggered device sizes. Two or three CMOS circuits are series-connected and then buffered by a BICMOS circuit. The series-connected CMOS circuits have decreasing device sizes to reduce the fan-out load of the CMOS circuits. BICMOS logic circuits offer improved circuit speeds compared with those obtainable by a pure CMOS logic. The improved speeds are due to the high drive capability of the bipolar transistors. BICMOS circuits have the advantage of improved performance at high loads. If the logic is not required for driving high loads, this advantage is minimal and may even be offset.

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Staggered High-Speed BICMOS Logic

The proposed scheme offers a very high BICMOS (BIpolar/Complementary Metal Oxide Silicon) circuit performance by staggered device sizes. Two or three CMOS circuits are series-connected and then buffered by a BICMOS circuit. The series-connected CMOS circuits have decreasing device sizes to reduce the fan- out load of the CMOS circuits. BICMOS logic circuits offer improved circuit speeds compared with those obtainable by a pure CMOS logic. The improved speeds are due to the high drive capability of the bipolar transistors. BICMOS circuits have the advantage of improved performance at high loads. If the logic is not required for driving high loads, this advantage is minimal and may even be offset. In addition, BICMOS circuits are area-consuming owing to the large number of devices they include and particularly owing to their internal wiring. The large number of devices included in BICMOS circuits limits the yield considerably. Therefore, the proposed scheme is aimed at obtaining maximum speeds by using a combination of CMOS and BICMOS and at reducing the number of BICMOS circuits with respect to area, while improving the yield. The pure CMOS circuits referred to below comprise only N- and P-FETs, whereas the BICMOS circuits comprise N- and P-FETs as well as bipolar NPN transistors. Both circuit types are present on the same chip. To achieve the aforementioned objectives, unloaded CMOS circuits are used wherever possible. Decreasing...