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Bit Slice Binary DECREMENT by One Circuit

IP.com Disclosure Number: IPCOM000034653D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Levy, JR: AUTHOR

Abstract

A combinatorial circuit which can decrement a binary input of any length by one can be made with a minimum number of transistors by the use of XNOR circuits configured as a two-input bit slice. This configuration allows very dense VLSI macros to be implemented while minimizing the fanout in each stage. (Image Omitted) Referring to Fig. 1, pins A0 and A1 represent binary input data. Pin D represents the decrement by one control input. Sum --SO and sum --S1 represent the binary output of the decrement by one circuit. The output sum --SO and sum --S1 will be equal to the input A0 and A1, minus one, when pin D is active (high). When pin D is low (inactive), the input appearing at pins A0 and A1 will appear at sum S0 and sum S1 unchanged.

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Bit Slice Binary DECREMENT by One Circuit

A combinatorial circuit which can decrement a binary input of any length by one can be made with a minimum number of transistors by the use of XNOR circuits configured as a two-input bit slice. This configuration allows very dense VLSI macros to be implemented while minimizing the fanout in each stage.

(Image Omitted)

Referring to Fig. 1, pins A0 and A1 represent binary input data. Pin D represents the decrement by one control input. Sum --SO and sum --S1 represent the binary output of the decrement by one circuit. The output sum --SO and sum --S1 will be equal to the input A0 and A1, minus one, when pin D is active (high). When pin D is low (inactive), the input appearing at pins A0 and A1 will appear at sum S0 and sum S1 unchanged. The truth table below denotes the signal states for all cases in the two-stage decrementer. As the stages are cascaded, the input appearing at the sum S0...Sn outputs will always be one less than the A0...An inputs when pin D is active (high), and will be the same as the A0...An inputs when pin D is inactive (low).

Figs. 2 and 3 depict the CMOS transistor implementation of the 2- bit decrementer slice for the odd bit and the even bit, respectively. TRUTH TABLE DECREMENT IN D A0 A1 S0 S1 DECREMENT OUT 0 0 0 0 0 0

1 0 0 0 0 1

0 1 0 1 0 0

1 1 0 0 0 0

0 0 1 1 1 0

1 0 1 1 0 0

0 1 1 1 1 0

1 1 1 0 1 0.

1

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