Browse Prior Art Database

Asynchronous Parallel Data Transfer Interface Technique

IP.com Disclosure Number: IPCOM000034654D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 4 page(s) / 158K

Publishing Venue

IBM

Related People

Westcott, GR: AUTHOR

Abstract

Data can be transferred asynchronously from a host data processing system to an output device on a simplified demand/response parallel interface without clocking signals and using parallel data transfer with only a few control and status signals. An arrangement of the interface controls between host system 1 and output device 2, such as a printer, is shown in Fig. 1. Asynchronous Data Interface Controls 3 generate the data request to the host through Interface Drivers and Receivers 4 and requests direct memory access (DMA) through block 5 to microprocessor unit (MPU) 6. Host data are (Image Omitted) then transferred under DMA control to memory 7. Output device 2 then accesses memory 7. The Asynchronous Data Interface Controls 3 also decode special characters, such as paper handling codes, that terminate data transfer.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 83% of the total text.

Page 1 of 4

Asynchronous Parallel Data Transfer Interface Technique

Data can be transferred asynchronously from a host data processing system to an output device on a simplified demand/response parallel interface without clocking signals and using parallel data transfer with only a few control and status signals. An arrangement of the interface controls between host system 1 and output device 2, such as a printer, is shown in Fig. 1. Asynchronous Data Interface Controls 3 generate the data request to the host through Interface Drivers and Receivers 4 and requests direct memory access (DMA) through block 5 to microprocessor unit (MPU) 6. Host data are

(Image Omitted)

then transferred under DMA control to memory 7. Output device 2 then accesses memory 7. The Asynchronous Data Interface Controls 3 also decode special characters, such as paper handling codes, that terminate data transfer. The generation of a request for data from an output device, the MPU response to the DMA request, and the host adapter data request interlock are shown in the timing diagram in Fig. 2. The circuit diagrams for most of the necessary signals and controls are seen in Figs. 3 and 4 with special character interrupt and data request in Fig. 3 and host data controls and interrupts 0 and 2 in Fig. 4. The control registers for storing various signals referred to are not illustrated. Strobe and DMA flip-flops in Fig. 3 block further data requests until a previous DMA cycle is complete. A print line for ou...