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Browse Prior Art Database

Content Addressable Memory Structures

IP.com Disclosure Number: IPCOM000034657D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 5 page(s) / 117K

Publishing Venue

IBM

Related People

O'Neil, EF: AUTHOR

Abstract

A content addressable memory cell structure with all p-channel field- effect transistor (FET) devices, one with n and p-channel devices, a simplified n-channel version of the n and p-channel cell and a dynamic cell with cross-coupled write devices is reported. Content addressable memories (CAM) have found application in data management, parallel processing and other associative applications (Image Omitted) where matching input data with stored information makes these memories useful as associative search address generators. Beside the attribute of matching data, CAM cells have full read, write and refresh capabilities. A conventional CAM cell uses static random access memory (SRAM) coupled to an exclusive NOR (XNOR) circuit to match input data with data stored in the CAM cell.

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Content Addressable Memory Structures

A content addressable memory cell structure with all p-channel field- effect transistor (FET) devices, one with n and p-channel devices, a simplified n-channel version of the n and p-channel cell and a dynamic cell with cross-coupled write devices is reported. Content addressable memories (CAM) have found application in data management, parallel processing and other associative applications

(Image Omitted)

where matching input data with stored information makes these memories useful as associative search address generators. Beside the attribute of matching data, CAM cells have full read, write and refresh capabilities. A conventional CAM cell uses static random access memory (SRAM) coupled to an exclusive NOR (XNOR) circuit to match input data with data stored in the CAM cell. To enhance density, a pseudo static charge amplifying cell and a XNOR circuit utilizing all p-channel FET devices are coupled to form a pseudo static content addressable memory (PSCAM) cell, shown in Fig. 1. Devices T5, T5A and T6 are p-channel FET devices used to perform the XNOR function. Alternatively, the XNOR circuit may be designed with n-channel devices. A pseudo static charge amplifying (PSCA) cell with local refresh (shown surrounded by a dashed line) is coupled to the XNOR to complete the PSCAM cell. Operation of a pseudo static charge amplifying cell (also known as a DRAM current gain cell with local refresh) is covered in the reference. The second pseudo static charge amplifying cell in Fig. 1 is needed because signals are differentially stored at each PSCAM cell. T1 and T2 and T1A and T2A have thresholds of -3 volts. All other p-channel devices are set at -1 volt. B0 and B1 are input bit lines driven to their appropriate logic level and a match line senses the XNOR results. Providing a charge amplifying cell with local refresh capability results in a storage cell design nearly equivalent to a SRAM cell and requires much less silicon area for each cell, leading to a more dense design.

(Image Omitted)

A match is accomplished by differentially driving the bit lines to a high potential and driving the match line to a high potential as shown in Fig. 2. If the bit lines B0 and B1 are charged to their logical levels, a bit line is lowered on one of the lines where the cell has a high potential stored, the match line is discharged and a mismatch is detected. A match occurs when the same data appears on the bit lines as that which is stored in the memory cell. A truth table follows:

B0 B1 Match

0 0 1

0 1 0

1 0 0

1

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1 1 1 A non-destructive read operation (timing chart not shown) is performed by discharging the bit lines to ground and raising the potential of the match line. The appropriate logic level will appear on the respective bit lines,
i.e., if node B is high (3.4 volts) and node BB is low (0.0 volts), the B1 line rises to VDD and B0 remains at "0.0" volts. Fig. 3 shows a write operation timing diagra...