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Random Pattern Test Strategy for Logic Surrounding Embedded Arrays

IP.com Disclosure Number: IPCOM000034665D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Forlenza, DO: AUTHOR [+2]

Abstract

The test strategy described in this article enhances random pattern testing of all logic peripheral to an embedded array. It does this by making all LSSD (level-sensitive scan design) patterns fully independent, thereby providing the ability to diagnose random pattern failures by post-test fault simulation plus an opportunity to use more efficient fault simulation techniques. Random pattern testing is increasingly employed in testing logic chips, especially those which are LSSD (level-sensitive scan design) [1]. Design tests already exist which provide for the complete and efficient random pattern test of LSSD logic chips 2, 3, 4.

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Random Pattern Test Strategy for Logic Surrounding Embedded Arrays

The test strategy described in this article enhances random pattern testing of all logic peripheral to an embedded array. It does this by making all LSSD (level-sensitive scan design) patterns fully independent, thereby providing the ability to diagnose random pattern failures by post-test fault simulation plus an opportunity to use more efficient fault simulation techniques. Random pattern testing is increasingly employed in testing logic chips, especially those which are LSSD (level-sensitive scan design) [1]. Design tests already exist which provide for the complete and efficient random pattern test of LSSD logic chips 2, 3, 4. Conventional random pattern tests will not, however, do the following without great difficulty when applied to chips containing arrays (embedded arrays): 1) test for all faults on array I/O (input/output),

2) perform fault simulation to evaluate test coverage, and

3) perform diagnosis of random pattern failures by

post-test

fault simulation (simulations limited only to failing

LSSD patterns) The disclosed test strategy resolves these problems, making it possible to test LSSD designs containing embedded arrays with random patterns. It provides a test for all faults on logic that surround the array, such that a fault simulator can efficiently evaluate test coverage and perform a diagnosis of failures. Memory cell testing is handled separately by an algorithmic (APG) test of all memory cells. Assuming LSSD design rules to apply, defined correspondence paths exist between each array I/O and a corresponding primary I/O and a corresponding primary I/O or LSSD latch. Prior to application of random pattern tests, the array will be initialized with weighted random values that will allow testing of all faults on the output side of the array. When multiple sets of weights are required, the arrays would be reinitialized with a new set of desired weighted random values. Thus, the array would be treated as pseudo primary inputs (PIs) and behave as read-only storage (ROS) during the random pattern test. Write lines of all arrays are held OFF to ensure LSSD pattern independence during application of the random pattern test. By treating arrays as pseudo PIs, faults on the output side of the array can be fully tested, leaving the problem of testing faults on the input side of the array. Initialization of the array and subsequent te...