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Motorola 68000 LSSD Write Mechanism Invention Implementation

IP.com Disclosure Number: IPCOM000034681D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Hinz, KC: AUTHOR [+2]

Abstract

A system clock is described which latches data from the Motorola 68000 data bus on a write operation in order to make these latches synchronous with the rest of the logic in an LSI module. The Motorola 68000 timings for the data bus are determined by the Motorola 68000 control tags. If the Motorola 68000 is running asynchronously with an IBM LSI chip and a system clock is needed to latch data from the Motorola 68000 data bus, the data bus timings do not guarantee valid data on a write operation from the Motorola 68000, when used in a system where the system clock frequency is below a frequency that is guaranteed to sample critical control tags and latch in valid data from the Motorola 68000. The logic used to guarantee a write operation from the Motorola 68000 is shown in Fig. 1. The latches are all LSSD L1/L2 pairs.

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Motorola 68000 LSSD Write Mechanism Invention Implementation

A system clock is described which latches data from the Motorola 68000 data bus on a write operation in order to make these latches synchronous with the rest of the logic in an LSI module. The Motorola 68000 timings for the data bus are determined by the Motorola 68000 control tags. If the Motorola 68000 is running asynchronously with an IBM LSI chip and a system clock is needed to latch data from the Motorola 68000 data bus, the data bus timings do not guarantee valid data on a write operation from the Motorola 68000, when used in a system where the system clock frequency is below a frequency that is guaranteed to sample critical control tags and latch in valid data from the Motorola 68000. The logic used to guarantee a write operation from the Motorola 68000 is shown in Fig. 1. The latches are all LSSD L1/L2 pairs. One assumption of this design is that the clock frequency used in the design is long enough that if a latch goes into metastability, it will settle to a known value by the time the next clock comes along. The data strobe signal is sampled by a latch L#1 to see when the data strobe(s) signal is asserted. The data strobe signal is asynchronous to the system clocks. If the latch goes metastable, it will settle out by the next C1. With L#1 in a logic 1 state, and L#2 in a logic 0 state, "data or clock gate" is active and can be used to gate valid data into a latch. The L#2 latch is set to a one...