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Monolithic Ceramic Substrate and Heat Sink for Integrated Circuit Packages

IP.com Disclosure Number: IPCOM000034685D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 51K

Publishing Venue

IBM

Related People

Powell, DO: AUTHOR

Abstract

A ceramic integrated circuit module having greatly enhanced heat dissipating powers is described in the following. Fig. 1 shows a schematic cross section of a typical embodiment of the module. Pins 1 are located on a 0.050-inch grid 1.3 inches square to accommodate 400 I/Os for a chip of approximately 0.5 inches square. The ceramic substrate is designed with an integrated heatsink. The ceramic used is either aluminum nitride (AlN) or silicon carbide (SiC). These materials have the advantages of high thermal conductivity and thermal expansions closely matched to that of silicon. The substrate is produced by injection (or other) molding, dry pressing, green state machining, or other known ceramic forming methods.

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Monolithic Ceramic Substrate and Heat Sink for Integrated Circuit Packages

A ceramic integrated circuit module having greatly enhanced heat dissipating powers is described in the following. Fig. 1 shows a schematic cross section of a typical embodiment of the module. Pins 1 are located on a 0.050-inch grid 1.3 inches square to accommodate 400 I/Os for a chip of approximately 0.5 inches square. The ceramic substrate is designed with an integrated heatsink. The ceramic used is either aluminum nitride (AlN) or silicon carbide (SiC). These materials have the advantages of high thermal conductivity and thermal expansions closely matched to that of silicon. The substrate is produced by injection (or other) molding, dry pressing, green state machining, or other known ceramic forming methods. The integrated circuit chip is back bonded to the substrate using known techniques such as eutectic bonding, soldering, epoxy bonding, etc. Back bonding with a metallic bond provides a high thermal conductance path from the chip to the substrate/heatsink. For eutectic or solder bonding, the substrate bonding site would be metallized using known methods. The bonding cavity shown is optional, and its purpose is to provide a more planar surface for attaching the decal or Tape Automated Bonding (TAB) interconnect.

(Image Omitted)

The chip to module I/O pin interconnection is provided either with a decal (shown), or a TAB lead carrier. In the case of a decal, the decal to chip connection is made using known controlled collapse chip carrier (C4) technology. The pins are inserted through holes in the decal and soldered to pads on the substrate and decal. In the case of a TAB, the chip leads are bonded using standard TAB technology, and the outer TAB leads are bonded to metallized circuit lines on the substrate which connect to pads around the I/O pins. The metallized pads (and circuitry, if required) on the substrate are produced by known methods such as Metallized Ceramic (MC) technology, plating and pho...