Browse Prior Art Database

Distributing Capacitance to Achieve Maximum Performance

IP.com Disclosure Number: IPCOM000034706D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Ganser, DD: AUTHOR [+3]

Abstract

The majority of the bus activity form a Motorola 68000 processor is read operations from memory. In performance-critical environments, any method of enhancing the read operation time is very valuable. Described herein is a way to move and distribute capacitance from critical nets to non-critical nets to reduce the time required to read data from memory. When reading data from RAM memory, the RAM modules drive the data onto a data bus which is gated through to the processor. The RAM modules will drive the data out within a specified amount of time from being selected. Whether the RAM data bus is lightly loaded with capacitance or heavily loaded to the maximum specification of capacitance, the RAM modules will drive the data out onto the data bus in the same time according to the specification. Fig.

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Distributing Capacitance to Achieve Maximum Performance

The majority of the bus activity form a Motorola 68000 processor is read operations from memory. In performance-critical environments, any method of enhancing the read operation time is very valuable. Described herein is a way to move and distribute capacitance from critical nets to non-critical nets to reduce the time required to read data from memory. When reading data from RAM memory, the RAM modules drive the data onto a data bus which is gated through to the processor. The RAM modules will drive the data out within a specified amount of time from being selected. Whether the RAM data bus is lightly loaded with capacitance or heavily loaded to the maximum specification of capacitance, the RAM modules will drive the data out onto the data bus in the same time according to the specification. Fig. 1 shows the system configuration with the processor, RAM, and the memory controller before the capacitance on the 68000 data bus was distributed. Executing a read from RAM memory using this configuration would occur by the RAM outputting data to the memory controller and the memory controller asserting the data onto the 68000 data bus. Using this configuration, the memory controller must drive the total capacitive load that is on the 68000 data bus.

(Image Omitted)

Fig. 2 shows the system configuration with the processor, RAM, and the memory controller after the capacitance on the 68000 data bus was distributed. Ex...