Browse Prior Art Database

ISDN Protocol

IP.com Disclosure Number: IPCOM000034710D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 89K

Publishing Venue

IBM

Related People

Gee, TW: AUTHOR [+2]

Abstract

Disclosed is a method for minimizing the frequency of a system clock while controlling the phase delay of a signal through a system. This technique should be useful in meeting phase delay requirements of ISDN. Synchronous logic depends on input signals being stable at the time that they are sampled (clocked). A finite time after the clock, the result of the logical function is available at an output (propagation delay). If a logical operation is composed of a series of N logical functions, the response of that system to given inputs is available after N clock periods; one clock pulse is required to transition each synchronous logic function. When the logical result is needed within T seconds, there must be a clock running at N/T hertz to insure that the result of the operation is finished when needed.

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ISDN Protocol

Disclosed is a method for minimizing the frequency of a system clock while controlling the phase delay of a signal through a system. This technique should be useful in meeting phase delay requirements of ISDN. Synchronous logic depends on input signals being stable at the time that they are sampled (clocked). A finite time after the clock, the result of the logical function is available at an output (propagation delay). If a logical operation is composed of a series of N logical functions, the response of that system to given inputs is available after N clock periods; one clock pulse is required to transition each synchronous logic function. When the logical result is needed within T seconds, there must be a clock running at N/T hertz to insure that the result of the operation is finished when needed.

(Image Omitted)

If each logical function uses a clock that is delayed by the propagation time of the function immediately ahead of it, (Fig. 1), the result will be ready N*(propagation delay) seconds later. Since N*(propagation delay)<<T, the signal is ready much earlier than required; the system "waits" and delivers the output at the appropriate time T. Note that with this scheme, the system clock runs at 1/T, not N/T. This alone will result in fewer EMC problems. Since the system clock is "smeared" out over N*(propagation delay) seconds, any radiation will be further reduced. In communications systems that run synchronous to incoming data, the system...