Browse Prior Art Database

High Performance 32-Bit ALU

IP.com Disclosure Number: IPCOM000034714D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Jacobs, MN: AUTHOR [+2]

Abstract

As the data width of an ALU (Arithmetic Logic Unit) is increased, the number of logic delay levels through the ALU also increases. To compensate for the additional levels of logic, either a faster logic technology has to be used or the cycle time of the ALU functions has to be increased. Because of cell count limitations, it is sometimes required to partition an ALU across more than one logic chip. The delay of a chip crossing in the ALU also requires that the cycle time has to be increased. Many ALU operations do not require additional logic delay levels as the ALU width increases. AND, OR, XOR, PASS LEFT, and PASS RIGHT operations require the same number of logic delay levels independent of the width of the ALU, since there is no carry required.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 77% of the total text.

Page 1 of 2

High Performance 32-Bit ALU

As the data width of an ALU (Arithmetic Logic Unit) is increased, the number of logic delay levels through the ALU also increases. To compensate for the additional levels of logic, either a faster logic technology has to be used or the cycle time of the ALU functions has to be increased. Because of cell count limitations, it is sometimes required to partition an ALU across more than one logic chip. The delay of a chip crossing in the ALU also requires that the cycle time has to be increased. Many ALU operations do not require additional logic delay levels as the ALU width increases. AND, OR, XOR, PASS LEFT, and PASS RIGHT operations require the same number of logic delay levels independent of the width of the ALU, since there is no carry required. Only operations, such as ADD or SUBTRACT, require additional levels in the carry logic as the width of the ALU increases. Instead of slowing down all ALU operations, this method allows the performance of non-carry operations in one cycle. Wide ALU operations that require a carry are performed in multiple cycles. Wide ALU operations that do not require a carry are performed in a single cycle. Other ALU operations, with or without a carry that do not involve a wide ALU also are performed in one cycle. The figure shows a high-level diagram of the design, which provides a carry latch between the ALU LO and ALU HI. By putting the latch between the two ALUs, wide or 32-bit ALU carry operations can...