Browse Prior Art Database

Readable Register With Bad Parity

IP.com Disclosure Number: IPCOM000034726D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Brey, TM: AUTHOR [+3]

Abstract

Generally, when a readable register that is parity checked detects a parity error it becomes unreadable and the error indication is signalled indicating data in the register is invalid. It becomes difficult to determine the source of this error if there are multiple levels between the register being read and the receiving register, as shown in the design of Fig. 1. In the design of Fig. 2, a position is reserved in the source register to assist in the isolation. When a parity error is detected within the source register, the register parity error bit of this reserved position is turned on and good parity is generated for the register as it is forwarded to the receiver.

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Readable Register With Bad Parity

Generally, when a readable register that is parity checked detects a parity error it becomes unreadable and the error indication is signalled indicating data in the register is invalid. It becomes difficult to determine the source of this error if there are multiple levels between the register being read and the receiving register, as shown in the design of Fig. 1. In the design of Fig. 2, a position is reserved in the source register to assist in the isolation. When a parity error is detected within the source register, the register parity error bit of this reserved position is turned on and good parity is generated for the register as it is forwarded to the receiver. In this manner, the receiver clearly identifies the source register as bad and does not suspect the intermediate registers as possible causes of the error, which would happen without this design.

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