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CMOS Semiconductor Memory Structural Modification to Allow Increased Memory Charge

IP.com Disclosure Number: IPCOM000034737D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 4 page(s) / 75K

Publishing Venue

IBM

Related People

Dennard, RH: AUTHOR

Abstract

A technique is described whereby a certain type of semiconductor structure, for dynamic memory cells using the CMOS technology, utilizes trench capacitors to store the signal voltage and is modified in such a way so as to allow a greater storage charge. Described is a relatively small change to the fabrication process which can reduce the maximum field in the storage capacitor by a factor of two. This allows a greater storage charge through the thinning of the insulator. Some newer types of dynamic random-access memory (RAM) cells, which use trench capacitors, store the signal voltage on an electrode inside the trench, while the surfaces outside of the trench are kept at a fixed potential. Fig. 1 shows a cross-section of the basic memory cell with the stored signal on the conductor inside of the trench.

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CMOS Semiconductor Memory Structural Modification to Allow Increased Memory Charge

A technique is described whereby a certain type of semiconductor structure, for dynamic memory cells using the CMOS technology, utilizes trench capacitors to store the signal voltage and is modified in such a way so as to allow a greater storage charge. Described is a relatively small change to the fabrication process which can reduce the maximum field in the storage capacitor by a factor of two. This allows a greater storage charge through the thinning of the insulator. Some newer types of dynamic random-access memory (RAM) cells, which use trench capacitors, store the signal voltage on an electrode inside the trench, while the surfaces outside of the trench are kept at a fixed potential. Fig. 1 shows a cross-section of the basic memory cell with the stored signal on the conductor inside of the trench. VDD is the supply voltage and VB is the increase in the well bias, supplied by a "substrate" generator, to provide back-gate bias on the p-channel array devices. The prior-art structure of Fig. 1 is such that the minimum stored voltage at the capacitor plate, when the wordline voltage is brought to ground potential, is higher than ground by the amount of the threshold drop Vt across the field-effect transistor (FET) portion of the cell. Moreover, Vt has a relatively large magnitude, due to the substrate

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sensitivity effect with the heavily doped n-well. The voltage swing on the capacitor, between the two stored signal levels, is only VDD - ¯Vt¯. However, the full supply voltage appears across the storage insulator when the positive level is written into the cell. This causes a maximum electric field of VDD/tox in this thin insulator. It is generally accepted that the ideal design of the dynamic RAM capacitor should have the fixed potential at one side of the capacitor midway between the two stored voltage levels on the other side [1]. Ideally, with wordline boosting to write 0 and VDD into the cell, the fixed potential should be at VDD/2. This will provide a maximum electric field magnitude of VDD/2 tox, which occurs for either of the two stored voltage levels. In some previous types of memory cells, unlike the cell shown in Fig. 1 the voltage level is stored on the outside of the trench and the fixed potential of the storage plate inside the trench can readily be set to VDD/2. This approach has been identified as a key element for future memory structures [2].

However, cells such as shown in Fig. 1 use the p+ substrate as the fixed electrode for the major component of the storage capacitance. These structures have many advantages since there is less interaction between one cell and another. However, the potential on this substrate cannot be raised above ground because it is common to the body of the n-channel devices; namely, it would cause grounded n+ sources to become forward biased. The concept described herein

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