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Automatic Unlimited Dynamic Memory Relocation

IP.com Disclosure Number: IPCOM000034744D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 5 page(s) / 34K

Publishing Venue

IBM

Related People

Einkauf, MA: AUTHOR

Abstract

An algorithm is disclosed which compensates for failed memory in a computer system. Memory is a vital component of any computer system. The failure of even a small portion of the computer's total memory severely limits the usefulness of the computer and often will completely disable it. Therefore, it is desirable to isolate such memory failures (faults) and compensate for them, so that the fault does not significantly impact the usefulness of the system. It is also desirable to perform such failure compensation automatically without involving the user. A process which will perform such failure compensation is described below.

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Automatic Unlimited Dynamic Memory Relocation

An algorithm is disclosed which compensates for failed memory in a computer system. Memory is a vital component of any computer system. The failure of even a small portion of the computer's total memory severely limits the usefulness of the computer and often will completely disable it. Therefore, it is desirable to isolate such memory failures (faults) and compensate for them, so that the fault does not significantly impact the usefulness of the system. It is also desirable to perform such failure compensation automatically without involving the user. A process which will perform such failure compensation is described below. Although this algorithm can be applied to various computer systems, the implementation shown here is for the IBM 80286 Expanded Memory Adapter/A, an adapter card providing additional memory for the IBM Personal System/2* computers.

The card features a Translate Table which serves to translate addresses provided by the computer into addresses which reference the Main Memory located on the card. The figure illustrates the function of the Translate Table. Computer address bits A23-A12 reference one of 4K (4096) 12-bit locations in the Translate Table. The contents of the 12-bit location (note only 9 bits are actually used), appended with computer address bits A11-A0, form the 21-bit address which references a single byte within Main Memory. Therefore, the contents of the Translate Table location corresponding to a particular computer address specify which byte in Main Memory corresponds to a particular computer address. Therefore, by changing the contents of a particular Translate Table location, the location of Main Memory corresponding to a particular computer address is also changed.

Thus, the Main Memory location is "relocated" if the corresponding Translate Table location contents are modified. This concept of a Translate Table is not new and is widely used in existing memory products. Methods requiring user intervention which employ programming of the Translate Table to provide fault isolation and compensation for a limited number of faults have also been used. However, this algorithm provides an automatic method of isolating and compensating for an unlimited number of faults. THE ALGORITHM The Translate Table on the card must be initialized (programmed) before the Main Memory is activated for general use by the computer. This involves programming the Translate Table to map the Main Memory into the appropriate computer address space, testing the Main Memory, and relocating any failing memory by modifying the contents of the Translate Table. Each 12-bit location in the Translate Table can reference one 4Kb block of Main Memory. To prevent a Translate Table location from referencing a 4Kb block of Main Memory, the location can be "inhibited" by placing a specific value in the contents of the location. Note that the 4096 Translate Table locations are sufficient to...