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Buried Contact Structure

IP.com Disclosure Number: IPCOM000034750D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 84K

Publishing Venue

IBM

Related People

Lu, NC: AUTHOR [+3]

Abstract

This publication describes a structure for a low resistance contact between a trench-filled poly-si and a diffusion in a TCI memory cell, or a low resistance contact between a gate poly-si and a diffusion. The new buried contact structure can be applied to any static RAM (random-access memory) cell to make contact between a silicided polysilicon gate to a silicided diffusion independent of doping polarities. At the same time, it also provides additional wiring capability. The structures and the processing sequence are described with reference to the drawings which show the technology used for two embodiments (a) and (b), as follows: (Image Omitted) Fig. 1(a) shows a TCI cell up to the point trenches are filled with polysilicon and planarized.

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Buried Contact Structure

This publication describes a structure for a low resistance contact between a trench-filled poly-si and a diffusion in a TCI memory cell, or a low resistance contact between a gate poly-si and a diffusion. The new buried contact structure can be applied to any static RAM (random-access memory) cell to make contact between a silicided polysilicon gate to a silicided diffusion independent of doping polarities. At the same time, it also provides additional wiring capability. The structures and the processing sequence are described with reference to the drawings which show the technology used for two embodiments (a) and (b), as follows:

(Image Omitted)

Fig. 1(a) shows a TCI cell up to the point trenches are filled with polysilicon and planarized. A polysilicon gate is defined, source/drain ion implants and drive-in are done, and oxide spacers are formed at the polysilicon gate sidewall. Fig. 1(b) shows the counterpart of a static RAM cell without trenches. The next step is to deposit a blanket metal such as 500 Ao Ti to form a TiSi2 layer as shown in Figs. 2(a) and 2(b). Before defining TiSi2 patterns, an additional masking step using lift-off scheme patterns 500Ao evaporated amorphous Si on top of the joining areas between the diffusion and polysilicon, as shown in Figs. 3(a) and 3(b). The standard salicide process will follow afterwards; first to form silicide (TiSi2) at 675oC 30' in N2, then selectively to etch away the unreacted Ti and to...