Browse Prior Art Database

Multiphase LSSD Clock Generation and Distribution

IP.com Disclosure Number: IPCOM000034762D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Buttimer, MD: AUTHOR

Abstract

Problems associated with the design of logic employing multiphase LSSD clocks are unpredictable maximum transit time for paths between latches in different phases and efficiency of clock distribution. This disclosure addresses these problems by using a single clock and clock steering latches to create multiple clocks and to simplify clock distribution through the use of binary-encoded gating signals. LSSD (Level Sensitive Scan Design) is described in detail by U.S. Patents 3,761,695, 3,783,254 and 3,784,907. A simple generalized two-phase clocked LSSD design is shown in Fig. 1. The two phases of clocks could be used to drive two basically separate, but related functional islands of logic.

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Multiphase LSSD Clock Generation and Distribution

Problems associated with the design of logic employing multiphase LSSD clocks are unpredictable maximum transit time for paths between latches in different phases and efficiency of clock distribution. This disclosure addresses these problems by using a single clock and clock steering latches to create multiple clocks and to simplify clock distribution through the use of binary- encoded gating signals. LSSD (Level Sensitive Scan Design) is described in detail by U.S. Patents 3,761,695, 3,783,254 and 3,784,907. A simple generalized two-phase clocked LSSD design is shown in Fig. 1. The two phases of clocks could be used to drive two basically separate, but related functional islands of logic. For example, Phase 3 clocks could be used to drive the processor instruction address sequencer, and Phase 1 clocks used in instruction execution. An implication of such a design is that the loading on the two clock phases (M for phase 1, and N for phase 3) will be directly proportional to the number of storage elements (latches and registers) used in each island, and are therefore likely to be quite different. Consequently, the maximum transit time available on certain data paths will be theoretically unpredictable until the design is complete - for example, from phase 1 register R1 through logic LA to phase 3 register R4.

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Another problem is that the two functional islands may well be logical macros and thus interwoven in the physical design of the chip, the two clock networks each absorbing dual wiring channels. The above problems are solved by using a single clock, clock- steering latches, and existing clock gates, as illustrated in Figs. 2 and 3. It should be noted that although the illustrations and descriptions are shown for two p...