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Modified Bus Arbitration for Rapid Interrupt Servicing

IP.com Disclosure Number: IPCOM000034764D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 59K

Publishing Venue

IBM

Related People

Anthony, BO: AUTHOR [+6]

Abstract

When building a computer system having multiple displays, communications, and DASD using the 80286, one problem is to allow long data transfers, which halt processor execution, while somehow still handling interrupts. Specifically, this means that the processor must be allowed to handle interrupts during long data transfers. This will allow service for time-critical interrupts like communications while still allowing large data transfers from disk. To be certain that interrupts will be processed rapidly, hardware was added to the interrupt controller. This hardware has the effect of changing the bus arbitration level for the processor when there is an interrupt. The higher bus arbitration level insures that the processor will be allowed to operate even if the interrupt occurs during a long data transfer.

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Modified Bus Arbitration for Rapid Interrupt Servicing

When building a computer system having multiple displays, communications, and DASD using the 80286, one problem is to allow long data transfers, which halt processor execution, while somehow still handling interrupts. Specifically, this means that the processor must be allowed to handle interrupts during long data transfers. This will allow service for time-critical interrupts like communications while still allowing large data transfers from disk. To be certain that interrupts will be processed rapidly, hardware was added to the interrupt controller. This hardware has the effect of changing the bus arbitration level for the processor when there is an interrupt. The higher bus arbitration level insures that the processor will be allowed to operate even if the interrupt occurs during a long data transfer. The processor will be allowed to operate because at an arbitration level higher than 15, all bus users essentially share the bus in a round- robin fashion. (The increase in priority will have no real effect if the bus is not busy at the time of interrupt.)

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The implementation of the increased priority was not simple or obvious, however. Two distinct problems presented themselves: when should the increased priority take effect, and what priority should be used. One solution seems to offer the desired features. This involves simply setting an interrupt priority level or threshold. Any interrupt priority above the threshold will be given a higher bus arbitration level. This provides the function required, without excessive hardware or software overhead for management. Interrupts are still handled in a logical priority sequence, and interrupts which exceed some threshold of priority also are given the higher bus arbitration level to ensure rapid handling. However, interrupts of a lower priority do not receive the higher bus arbitration level, and therefore they will not interrupt data transfers. See Fig. 1 for a picture of the interrupt controller hardware. Up to 16 hardware interrupt lines are first input to the priority assignment stage (1). The priority assignment stage can be programmed so that any input line can activate any output line. The 16 lines from the priority assignment stage then enter the priority encoder (2). Based upon which input line was active, the encoded output is a 4-bit binary number. This number is the encoded representation of the prior ity associated with an input line. The encoded priority then enters the representation of the priority associated with an input line. The en...