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Dual Port Input/Output System Processor With a Fast Path for Input/Output Attachments

IP.com Disclosure Number: IPCOM000034795D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 59K

Publishing Venue

IBM

Related People

Chisholm, DR: AUTHOR [+2]

Abstract

A technique is described whereby a dual port communications input/output (I/O) system processor provides a "Fast Path" operational architecture. The "Fast Path" enables an alternate random access storage communications path to accommodate a variety of subsystem I/O bus attachments. A typical I/O attachment connects to subsystem I/O bus 10, as shown in Fig. 1, within an I/O subsystem. Device interface control 11 and device drivers/receivers 12 are unique to a particular subsystem I/O bus attachment and random-access memory (RAM) data buffer 13 and RAM control unit 14 are not present on all attachments, but are required for "Fast Path" operation. The implementation of the "Fast Path" concept is shown in Fig.

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Dual Port Input/Output System Processor With a Fast Path for Input/Output Attachments

A technique is described whereby a dual port communications input/output (I/O) system processor provides a "Fast Path" operational architecture. The "Fast Path" enables an alternate random access storage communications path to accommodate a variety of subsystem I/O bus attachments. A typical I/O attachment connects to subsystem I/O bus 10, as shown in Fig. 1, within an I/O subsystem. Device interface control 11 and device drivers/receivers 12 are unique to a particular subsystem I/O bus attachment and random-access memory (RAM) data buffer 13 and RAM control unit 14 are not present on all attachments, but are required for "Fast Path" operation. The implementation of the "Fast Path" concept is shown in Fig. 2, where three operational units are added to the subsystem I/O bus attachment: direct memory access control (DMAC) unit 15; system I/O bus control unit 16; and message and packet (PKT) buffers 17, so as to connect directly to system I/O bus 18. The logic within system I/O bus control unit 16 and its associated message and PKT buffers 17 provide the initialization (normally of I/O system processor's) by way of direct select messages on system I/O bus 18. This enables the sending and receiving of messages, and in conjunction with DMAC unit 15, to transfer data packets to and from the host computer system storage from RAM data buffers, by way of system I/O bus 18. The "Fast Path" attachments are controlled by means of a microprocessor such that the control code, loaded during the initial machine load (IML) phase, will appear, from the host systems point of view, as a separate I/O system processor with self-loading capabilities. The actual control code, loaded for the "Fast Path" attachment, occurs when the I/O system processor is 'down loaded'. The microprocessor communicates with the "Fast Path" subsystem I/O bus across subsystem I/O bus 10, as it does with all subsystem I/O bus attachments within its subsystem, for execution of self-testing diagnostics. Subsystem I/O bus 10 is used in operational mode only to set up the control logic counters and pointers in the "Fast Path" attachment for initiation of data transfers across system I/O bus 18 and for the processing of ending interrupts and status controls. This provides greater data throughput for the device and eliminates subsystem I/O bus traffic and DMA interference with I/O system microprocessor cycles. In actual operation, the I/O system processors drive and receive their subsystem I/O bus information for communications with the subsystem I/O bus attachments that they control. Subsystem I/O bus attachments control various device and communication interface devices, such as low end direct access storage devices (DASDs) asynchronous and bisynchronous communications, and local area networks (LANs). The subsystem I/O bus attachments vary in function, cost, bandwidth requirements and I/O system...