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Signal Synchronization, Latching and Arbitrary Priority Assignment When Two Signals Are Coincident

IP.com Disclosure Number: IPCOM000034803D
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Leininger, JC: AUTHOR

Abstract

This article describes a circuit arrangement which provides the means to synchronize two asynchronous signals by clocking them through three level-sensitive scan design (LSSD) latches to eliminate oscillations and metastability. If the two signals become active during the same half cycle, the priority will be determined by which half cycle the signals went active. Fig. 1 shows the latch and clock sequences necessary to accomplish the desired function. Latches 5 and 6 have clocks that are always active and data flushes through them without any latching taking place. Direct memory access (DMA) 1 request is clocked sequentially into latches 1, 2 and 4. Prior to latch 4 is an AND circuit 3 that will only allow latch 2 to be clocked into latch 4 if no DMA 2 cycle (latch 10) is present.

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Signal Synchronization, Latching and Arbitrary Priority Assignment When Two Signals Are Coincident

This article describes a circuit arrangement which provides the means to synchronize two asynchronous signals by clocking them through three level-sensitive scan design (LSSD) latches to eliminate oscillations and metastability. If the two signals become active during the same half cycle, the priority will be determined by which half cycle the signals went active. Fig. 1 shows the latch and clock sequences necessary to accomplish the desired function. Latches 5 and 6 have clocks that are always active and data flushes through them without any latching taking place. Direct memory access (DMA) 1 request is clocked sequentially into latches 1, 2 and 4. Prior to latch 4 is an AND circuit 3 that will only allow latch 2 to be clocked into latch 4 if no DMA 2 cycle (latch 10) is present.

Similarly DMA 2 is clocked into latches 7, 9 and 10 sequentially with AND circuit 8 passing the signal into latch 9 if a DMA 1 cycle is not present. AND circuit 8 and latch 9 may glitch if both the DMA 1 and DMA 2 requests occur during the time period "A" shown in Fig. 2 which is a timing chart showing input signal priority. However, latch 9 will settle out before latch 10 is clocked. In Fig. 1 the shift register latches (SRLs) (L1 and L2 pair) are shown as polarity hold latches. Set/reset latches can be substituted for the polarity hold latches but they require more circuits. Both DMA 1 a...