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Digital RAS/CAS Generation for Dynamic Memories

IP.com Disclosure Number: IPCOM000034867D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Bartlett, JS: AUTHOR [+2]

Abstract

In order for a Dynamic Memory module (DRAM) to be used in any design, two unique signals, RAS* (Row Address Strobe) and CAS* (Column Address Strobe), must be provided to the memory modules. RAS* is used to latch the row address from the address lines, while CAS* is used to latch the column address. There are two basic methods for generating these signals: 1. The signals are provided by a dynamic RAM controller. This method is usually the most expensive way to generate the signals. 2. The signals are generated using a TTL delay line and some "glue" logic. This is a less expensive method, but it is still costly for small systems. Also, this method becomes ineffective if any type of integration is to be implemented (i.e.

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Digital RAS/CAS Generation for Dynamic Memories

In order for a Dynamic Memory module (DRAM) to be used in any design, two unique signals, RAS* (Row Address Strobe) and CAS* (Column Address Strobe), must be provided to the memory modules. RAS* is used to latch the row address from the address lines, while CAS* is used to latch the column address. There are two basic methods for generating these signals: 1. The signals are provided by a dynamic RAM

controller. This method is usually the most

expensive way to generate the signals.

2. The signals are generated using a TTL delay line

and some "glue" logic. This is a less expensive

method, but it is still costly for small systems.

Also, this method becomes ineffective if any type

of integration is to be implemented (i.e., PLAs,

gate arrays, standard cell, etc.) because the

delay line is an analog device. If material cost and/or integration is not an issue, either of the above methods would be an effective way to generate RAS* and CAS*. However, since cost usually is a big factor in low-end systems and integration is becoming more and more commonplace, another method is desirable. This following method is low-cost and easy to integrate into a custom chip or PLA.

(Image Omitted)

Fig. 1 is a block diagram of a dynamic RAM circuit that will interface to an Intel 8088/80188-based system, but conceptually can be applied to any processor-based system. The block labeled "RAS/CAS Generation Logic" is comprised of sequential and combinational logic and is expanded in Fig. 2. This portion of the block diagram replaces either the Dynamic RAM Controller or the delay-line circuit mentioned above. It is very inexpensive compared to either of the other alternatives, and it is completely digital which means it can be integrated into a custom chip or PLA with ease. In this type of implementation, it is assumed that one channel of the internal 80188 DMA will be dedicated to refresh of the DRAM. In systems which use self-refreshing DRAMs or have guaranteed periodic memory accesses, this is not a requirement. The inputs necessary for the RAS/CAS circuitry in Fig. 1 are signals that are generated by the 8088/80188. Status signals S0*, S1*, and S2* are decoded so that PRAS* (preliminary RAS) becomes active only during a memory cycle (i.e. ALE is low). The status signals are used, instead of the RD* (Read...