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Chip Temperature Leveling of Multi-Chip Modules After Encapsulation

IP.com Disclosure Number: IPCOM000034873D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Edwards, DL: AUTHOR [+2]

Abstract

Junction temperatures of semiconductor chips in a multi-chip module are controlled, and maintained within thermal specification, by adjusting the thermal resistances of the module after encapsulation. Typical high-performance cooling approaches integrate the cold plate and TCM hat into a single part. As a consequence of manufacturing tolerances on the chip and on the cooling hardware, the range of chip temperatures is very difficult to control without knowing the actual power dissipations and physical dimensions of the parts. The thermal consequences of these "actual" quantities are known only after the module is encapsulated with its cooling hardware.

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Chip Temperature Leveling of Multi-Chip Modules After Encapsulation

Junction temperatures of semiconductor chips in a multi-chip module are controlled, and maintained within thermal specification, by adjusting the thermal resistances of the module after encapsulation. Typical high-performance cooling approaches integrate the cold plate and TCM hat into a single part. As a consequence of manufacturing tolerances on the chip and on the cooling hardware, the range of chip temperatures is very difficult to control without knowing the actual power dissipations and physical dimensions of the parts. The thermal consequences of these "actual" quantities are known only after the module is encapsulated with its cooling hardware. The drawing illustrates a control scheme applied, for example, to an integrated multi-chip module having any suitable means 1 for conducting heat to convective pin fins 2 from chips 3, 4 and 5 having nominal, maximum, and minimum power, respectively. A plate 6 supports the pin fins and separates the chip space from the coolant space. A removable cover 7 forms part of the enclosure for the coolant space. Thermal control is achieved by the use of caps 8 and sleeves 9 on the pin fins. The nominal power chip has the sleeves mounted at the base of the pin fins, thereby increasing the conduction length between the chip and the water. For maximum power chips, caps are placed over the pins which force the coolant to pass through the base of the pin fins at...