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DRAM Test Time Reduction Via Sequential Array Select Mode

IP.com Disclosure Number: IPCOM000034876D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Ellis, WF: AUTHOR [+2]

Abstract

A method is shown for minimizing the peak noise on power distribution busses in a partitioned DRAM array during array test. (Image Omitted) In some DRAM designs, test functions are integrated into the chip design to realize a test time reduction. Fig. 1 shows a typical DRAM architecture which may represent an entire chip or a sub-array. In some DRAM designs, one fourth of the array is selected at a time to reduce power and noise on the Vdd/Gnd busses. Implementation of the test time reduction can be to either write multiple bits to each sub-array or set the entire chip (all four arrays) at once and then write/read multiple column bits. When the full chip array set mode is used, the design must be capable of handling the loading while maintaining signal margins.

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DRAM Test Time Reduction Via Sequential Array Select Mode

A method is shown for minimizing the peak noise on power distribution busses in a partitioned DRAM array during array test.

(Image Omitted)

In some DRAM designs, test functions are integrated into the chip design to realize a test time reduction. Fig. 1 shows a typical DRAM architecture which may represent an entire chip or a sub-array. In some DRAM designs, one fourth of the array is selected at a time to reduce power and noise on the Vdd/Gnd busses. Implementation of the test time reduction can be to either write multiple bits to each sub-array or set the entire chip (all four arrays) at once and then write/read multiple column bits. When the full chip array set mode is used, the design must be capable of handling the loading while maintaining signal margins. If a chip design is optimized for partial array select, but full array select is used for test, then the least positive up level and most positive down level signals must be relaxed for test mode due to power buss noise. A new mode, sequential array select (SAS), will reduce peak currents, reduce test time and also has the potential, if implemented in a system environment, to improve refresh time and array availability. In the SAS mode, the array is sequentially set by quadrant. The architecture used is shown in Fig. 2. The word address most significant bit (MSB) and next most significant bit (NMSB), i.e., An and An-1 respectively, and SAS mode lines are...