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Self-Aligned Gate Mosfets With Low-Temperature Gate Material

IP.com Disclosure Number: IPCOM000034878D
Original Publication Date: 1989-Mar-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 59K

Publishing Venue

IBM

Related People

Nguyen, TN: AUTHOR [+2]

Abstract

Self-aligned MOSFET transistors are widely used in current integrated circuits because of their high speed and high density advantages. The fabrication of such transistors requires that the gate be patterned early in the processing cycle to act as a mask for source and drain implants and that it is compatible to all subsequent processing steps. This process compatibility condition imposes a host of difficult requirements on the gate material, such as high melting temperature, good thermal and chemical stability with gate insulator, and low diffusivity in the gate insulator. In addition, the gate material has to meet important electrical requirements, such as low resistivity and suitable work function.

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Self-Aligned Gate Mosfets With Low-Temperature Gate Material

Self-aligned MOSFET transistors are widely used in current integrated circuits because of their high speed and high density advantages. The fabrication of such transistors requires that the gate be patterned early in the processing cycle to act as a mask for source and drain implants and that it is compatible to all subsequent processing steps. This process compatibility condition imposes a host of difficult requirements on the gate material, such as high melting temperature, good thermal and chemical stability with gate insulator, and low diffusivity in the gate insulator. In addition, the gate material has to meet important electrical requirements, such as low resistivity and suitable work function. As a result of all these conditions, many metals which are excellent candidates from a device physics point of view cannot qualify for the self-aligned gate application. Heavily doped polysilicon has become commonly used due to its excellent process compatibility although its electrical properties are just adequate. The advancement of integrated circuit technology, however, places more and more stringent demands on the gate material and pushes heavily doped polysilicon to its limit. Problems, such as high resistance, ragged edge in fine lines, dopant penetration through gate oxide, etc, must be solved if the current self-aligned polysilicon gate technology is to be extended to future generations of VLSI devices. This article describes a method for fabricating self-aligned gate transistors in which the gate material is deposited and patterned after the formation of source and drain junctions. It relies on the sidewall technique. A dummy gate made of oxide, for instance, serves as an implant mask. The sidewalls of the gate remain in place after the dummy gate is removed. These sidewalls are then used later in the process to define the real gate.

The method eliminates the problems associated with the polysilicon gate technology, as mentioned above. In addition, the device performance can be improved significantly by selecting an optimal gate material from many possible candidates that now become applicable because of the removal of the high temperature requirement. A detailed process embodiment of the self-alignment scheme is now given. Fig. 1 shows the cross-sectional and top views of a transistor area which has been defined by a planar isolation technique, such as a shallow trench filled with oxide. The gate insulator is formed, then followed by blanket CVD deposition of a thin (<200 Ao) nitride layer and a thick (1000 Ao or more, depending on the technology) oxide overlayer. The nitride layer serves as an etch stop for a subsequent etching step, but it can also be used as part of a dual-dielectric gate insulator, if needed. The thick oxide layer is used as a mask for source/drain implants. The following processing steps are carried out to make MOSFET circuits: Step 1. Sourc...