Browse Prior Art Database

Bit Line/Word Line Boost Circuit

IP.com Disclosure Number: IPCOM000034897D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 86K

Publishing Venue

IBM

Related People

Ellis, WF: AUTHOR [+3]

Abstract

A post sense bit and word line boost circuit design is shown which enhances the margins in advanced DRAMs and protects the cells against alpha particle radiation and leakage induced noise. (Image Omitted) As semiconductor process tolerances improve, greater levels of integration on a chip result. Cell areas and signal margins are reduced and stored "1" levels become more sensitive to alpha particles and leakage induced noise. Implementation of a post sense bit line and word line boost design will minimize this problem. At the beginning of a row address select (RAS) restore, the selected word line is boosted to at least a VT above Vdd and simultaneously the high bit lines are actively clamped to Vdd. This results in a full "1" level being written into the cell. Referring to Fig.

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Bit Line/Word Line Boost Circuit

A post sense bit and word line boost circuit design is shown which enhances the margins in advanced DRAMs and protects the cells against alpha particle radiation and leakage induced noise.

(Image Omitted)

As semiconductor process tolerances improve, greater levels of integration on a chip result. Cell areas and signal margins are reduced and stored "1" levels become more sensitive to alpha particles and leakage induced noise. Implementation of a post sense bit line and word line boost design will minimize this problem. At the beginning of a row address select (RAS) restore, the selected word line is boosted to at least a VT above Vdd and simultaneously the high bit lines are actively clamped to Vdd. This results in a full "1" level being written into the cell. Referring to Fig. 1, the bit line/word line boost (BLWLB) circuit consists of a pre-charge, trigger and disable front end logic block, a creepless clock driver, a word line boost circuit and bit line boost clock pulse (BLBP) output. While the word line boost circuit is boosting the selected word line a VT above Vdd, the BLBP signal is also driving the bit line boost circuits to actively clamp the high bit line to Vdd. Referring to Fig. 2 for circuit timing, when the chip is in standby or restore mode, the restore clocks RASNP and WTCRP are also high (Vdd). With WTCRP high, devices T2D, T2P, T2 and T36 are on, actively clamping their respective drains to ground. Also, devices T19 is on and actively clamping node N2D to Vdd - VT . As a result, the creepless clock is disabled with output BLBP actively clamped to ground through device T22. The plate of capacitor C7 (node N7) is pre-charged to Vdd through device T23. Thus, the BLWLB circuit is in a restore state and no power is consumed. When the chip is selected, the RAS chip input falls to its active low level. At this time, the restore clocks (RASNP & WTCRP) are disabled and fall to ground, turning off the before mentioned devices. Later the word line driver fires (decoded such that VW1 rises while VW2 is clamped to ground) followed by the DWLP clock firing. At this time the selected word and dummy word lines are charged and the sense latches are set. Also, the word line boost circuit for VW1 is precharged...