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Self-Test Feature for On-Chip Error Correction Code System

IP.com Disclosure Number: IPCOM000034899D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Fifield, JA: AUTHOR [+2]

Abstract

True (T) and complement (C) outputs from parity generators of an error correction code (ECC) system are valid if they are of opposite polarity. Exclusive OR (XOR) circuits are added to a standard ECC system to provide an error signal to a test pad and to a test register when invalid output (same polarity output) is found on a T/C line pair. Defects, such as a logic gate stuck at one level or a T or C line shorted to one level, are detected and an error signal is stored in the test register. Thus, ECC system self test results may be accessed after complete testing of a pin limited dynamic random-access memory (DRAM) package.

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Self-Test Feature for On-Chip Error Correction Code System

True (T) and complement (C) outputs from parity generators of an error correction code (ECC) system are valid if they are of opposite polarity. Exclusive OR (XOR) circuits are added to a standard ECC system to provide an error signal to a test pad and to a test register when invalid output (same polarity output) is found on a T/C line pair. Defects, such as a logic gate stuck at one level or a T or C line shorted to one level, are detected and an error signal is stored in the test register. Thus, ECC system self test results may be accessed after complete testing of a pin limited dynamic random-access memory (DRAM) package. Referring to the figure, when there are no faults in the ECC circuitry, opposite polarity signals result on all T/C output line pairs of the standard ECC system when data and check bit inputs 2 are supplied to parity generators 4,6,8, and 10. Each T/C pair is connected to a two input exclusive NOR (XNOR) circuit which provides a zero output when T/C line pairs carry signals of opposite polarity and a one, or error signal, if a T/C line pair carries signals of the same polarity. If one or more of the XNORs, e.g., 12, 14, 16, 18, provides a one signal to multi-input OR circuit 20, an error signal is sent to test pad 22 and to test register 24. Test results stored in register 24 may be accessed by input to address pads 26 through address decode circuit 28, thus triggering data in the regi...