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Complementary Metal Oxide Silicon Off-Chip Driver With Electrostatic Discharge Protection

IP.com Disclosure Number: IPCOM000034902D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Gray, KS: AUTHOR [+2]

Abstract

By using one channel of a multiple channel p-type pull-up transistor to bypass output impedance matching resistors, a direct path for electrostatic discharge is formed from a driver output line to the high voltage supply (VDD). This low resistance path to VDD, in addition to low resistance paths to ground provided by existing protect diodes in downstream circuits, results in improved electrostatic discharge (ESD) protection of off-chip driver (OCD) circuits. Referring to the figure, output A from the main portion 2 of a complementary metal oxide silicon (CMOS) OCD circuit is connected to the gate of multiple channel n-type pull-down transistor Tn. All channels of the multiple channel device Tn are connected from impedance matching, pull-down resistor Rdn to ground. Therefor, transistor Tn is shown as a single device.

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Complementary Metal Oxide Silicon Off-Chip Driver With Electrostatic Discharge Protection

By using one channel of a multiple channel p-type pull-up transistor to bypass output impedance matching resistors, a direct path for electrostatic discharge is formed from a driver output line to the high voltage supply (VDD). This low resistance path to VDD, in addition to low resistance paths to ground provided by existing protect diodes in downstream circuits, results in improved electrostatic discharge (ESD) protection of off-chip driver (OCD) circuits. Referring to the figure, output A from the main portion 2 of a complementary metal oxide silicon (CMOS) OCD circuit is connected to the gate of multiple channel n-type pull- down transistor Tn. All channels of the multiple channel device Tn are connected from impedance matching, pull-down resistor Rdn to ground. Therefor, transistor Tn is shown as a single device. A p-type multiple channel pull-up transistor Tp is shown as two transistors Tp1 and Tpr in a dashed enclosure. The channel of Tp1 is connected from Vdd to output node OUT. Transistor Tpr contains the channels which remain connected as usual from VDD to impedance matching pull-up resistor Rup. Output B from the OCD 2 is connected as usual to the gate of Tp, shown as individual gates to Tp1 and Tpr. This results in a low resistance path from OUT directly to VDD, bypassing resistor Rup. Voltage spikes of either polarity at node OUT are limited in amplitude by exis...