Browse Prior Art Database

Defect Current Elimination in Battery Back-Up Random-Access Memories

IP.com Disclosure Number: IPCOM000034906D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Dreibelbis, JH: AUTHOR [+3]

Abstract

By means of opening a fuse between the bit line restore voltage supply (Vr) and the bit line restore devices, a defect short existing between a bad bit line and ground can not cause current to flow through the restore devices during standby. Thus, when redundant bit lines are activated to replace a defective bit line in a battery back-up random access memory (RAM), defect originated parasitic standby current is avoided by blowing the fuse in the array segment having the bad bit line. Referring to the figure, a bit line restore circuit comprised of p-type devices T1, T2, and T3 is attached to true bit line 2 and complement bit line 4. Restore voltage Vr is supplied to lines 2 and 4 when restore input R is off. Input R is off for a short restore phase of active cycles but is off throughout standby periods.

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Defect Current Elimination in Battery Back-Up Random-Access Memories

By means of opening a fuse between the bit line restore voltage supply (Vr) and the bit line restore devices, a defect short existing between a bad bit line and ground can not cause current to flow through the restore devices during standby. Thus, when redundant bit lines are activated to replace a defective bit line in a battery back-up random access memory (RAM), defect originated parasitic standby current is avoided by blowing the fuse in the array segment having the bad bit line. Referring to the figure, a bit line restore circuit comprised of p-type devices T1, T2, and T3 is attached to true bit line 2 and complement bit line 4. Restore voltage Vr is supplied to lines 2 and 4 when restore input R is off. Input R is off for a short restore phase of active cycles but is off throughout standby periods. A defect in any RAM cell connected to the bit line pair 2 and 4 may result in a short to ground. An unacceptable current drain from the Vr supply during standby in RAMs having battery back-up can therefore occur. When a defect is identified to exist in circuits attached to either bit line 2 or 4, fuse F is blown at the time of spare element selection, thus avoiding defect originated parasitic standby current.

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