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Fully Testable Selector Circuit for a Multiport Latch

IP.com Disclosure Number: IPCOM000034916D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Oakland, SF: AUTHOR

Abstract

By means of a priority selector circuit for a multiport latch or register, simultaneous multiple port selection is avoided during testing. This priority selector also allows random pattern (self) testing of multiport circuits. Referring to the figure, port selection inputs 2, 4, 6, and 8 go to three logic gates which assure a port selection signal at only one of output ports 10, 12, 14, or 16. The circuit for port selection inputs 6 and 8 is identical to the circuit for port selection inputs 2 and 4. Input 2 goes through an inverter I into one input of a NOR gate 20 and input 4 is one input to a NAND gate 24. Port select output 10 is the output of NOR 20 and the signal at output port 12 is the inverted output of NAND 24. If additional ports exist in the circuit to be tested, the circuit is repeated as necessary.

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Fully Testable Selector Circuit for a Multiport Latch

By means of a priority selector circuit for a multiport latch or register, simultaneous multiple port selection is avoided during testing. This priority selector also allows random pattern (self) testing of multiport circuits. Referring to the figure, port selection inputs 2, 4, 6, and 8 go to three logic gates which assure a port selection signal at only one of output ports 10, 12, 14, or 16. The circuit for port selection inputs 6 and 8 is identical to the circuit for port selection inputs 2 and 4. Input 2 goes through an inverter I into one input of a NOR gate 20 and input 4 is one input to a NAND gate 24. Port select output 10 is the output of NOR 20 and the signal at output port 12 is the inverted output of NAND 24. If additional ports exist in the circuit to be tested, the circuit is repeated as necessary. If Inhibit All Ports input 18 is active (at logic value 1), then all outputs 10, 12, 14, and 16 are inactive (at logic value 0), regardless of logic values at inputs 2, 4, 6, 8. The value of 1 at input 18 causes a value of 0 at the output of NOR gates 20 and 22, which forces outputs of NAND gates 24 and 26 to logic value 1. Similar propogation through NOR gates 28 and 30 and NAND gates 32 and 34 forces successive outputs 14 and 16 to be inactive. If input 18 is inactive and port selection input 2 is active, then port select output 10 is active and all other port select outputs 12, 14, and 16 are inacti...