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Error Detection for Pipeline Clocking Circuitry

IP.com Disclosure Number: IPCOM000034918D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Hanna, SD: AUTHOR

Abstract

This article describes a system clock design including checking the interconnections between a clock generation module and a data or address pipeline module. It also provides a second check for the clock generation state machine. Some of the clock generation state machine output signals are checked by being independently generated and compared to the signals. The duplication uses a different generation method from the clock generation logic. This described technique is valuable because it is difficult to design error checks for clocking and control signals. The technique is demonstrated for two different applications. The master clock generator has one feedback signal from the slave that it compares with its internally generated prediction of what the feedback should be.

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Error Detection for Pipeline Clocking Circuitry

This article describes a system clock design including checking the interconnections between a clock generation module and a data or address pipeline module. It also provides a second check for the clock generation state machine. Some of the clock generation state machine output signals are checked by being independently generated and compared to the signals. The duplication uses a different generation method from the clock generation logic. This described technique is valuable because it is difficult to design error checks for clocking and control signals. The technique is demonstrated for two different applications. The master clock generator has one feedback signal from the slave that it compares with its internally generated prediction of what the feedback should be. The first feedback signal is CYCCNT (a cycle count feedback signal from the address generation module that is controlled by CLKA and CLKB). The signal CYCCNT is used in conjunction with ADDRVAL (an indication that the addresses are valid and ready for use) to check both the clocks and the address valid signal. This checking is done at a cost of one additional I/O per module and a small amount of additional logic. CYCCNT starts at a known state and then toggles every time a new address is generated. The Pipelined Functional Logic module is driven by four clock enable signals and two main system clock signals. The Pipelined module sends a CYCCNT2 (Cyc...