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Efficient Use of Redundant Bit Lines for Yield Optimization

IP.com Disclosure Number: IPCOM000034919D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Hiltebeitel, N: AUTHOR [+4]

Abstract

By using an architecture that permits a single data line to pass through all input/output (I/O) arrays and by the addition of fuses for decoding failed bit lines in all possible arrays on a chip, redundant bit lines may replace any failed bit line in any array. Thus, redundant bit lines not needed for one array are available as replacements for an array having more than one failed bit line. Referring to the figure, a memory is segmented into four arrays 2, 4, 6, and 8 and has 4 groups of redundant bit lines accessible through switches contained in blocks 10, 12, 14, and 16. Data lines 32, 34, 36, 38 and redundant data lines 28, 30, 40, 42 can be connected to all arrays through multiplexers (MUXs) 18, 20, 22 via lines 44, 46, 48, 50.

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Efficient Use of Redundant Bit Lines for Yield Optimization

By using an architecture that permits a single data line to pass through all input/output (I/O) arrays and by the addition of fuses for decoding failed bit lines in all possible arrays on a chip, redundant bit lines may replace any failed bit line in any array. Thus, redundant bit lines not needed for one array are available as replacements for an array having more than one failed bit line. Referring to the figure, a memory is segmented into four arrays 2, 4, 6, and 8 and has 4 groups of redundant bit lines accessible through switches contained in blocks 10, 12, 14, and 16. Data lines 32, 34, 36, 38 and redundant data lines 28, 30, 40, 42 can be connected to all arrays through multiplexers (MUXs) 18, 20, 22 via lines 44, 46, 48, 50. Lines 44, 46, 48, and 50 connect to input pad IN through receiver 24 and to output pad OUT through driver 26. Redundant bit line switches in blocks 10, 12, 14, 16 are controlled from redundant fuse block and decoder 52 via lines 58, 60, 64, 66 respectively. Fuse block and decoder 52 also controls MUXs 18, 22, and 20 via lines 56, 54, and 62 respectively. The control lines 54, 56, and 62 are also used during normal operation to pass data to and from arrays via appropriate devices e.g. receiver 24 or driver 26. During testing, appropriate fuses in block 52 are blown to steer data addressed to a bad bit line to a good, redundant bit line available anywhere in the four arrays 2,...