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Asynchronous Digital Filter Interface Design

IP.com Disclosure Number: IPCOM000034921D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 29K

Publishing Venue

IBM

Related People

Vogelsberg, RE: AUTHOR

Abstract

This article describes an interface between an unclocked (asynchronous) input signal and a clocked digital subsystem. It provides sampling and synchronization of the input signal through two levels of clocked latches which, in turn, align the input signal with the digital subsystem clocks and resolve any potential metastable latch states that may occur during the synchronizing process. A feature of this design is additional, parallel logic that provides noise rejection capabilities to the synchronizing circuit. Many logic designs require an asynchronous input signal to be synchronized to a locally clocked logic subsystem, accompanied with a requirement to remove noise from the input prior to sampling the input signal.

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Asynchronous Digital Filter Interface Design

This article describes an interface between an unclocked (asynchronous) input signal and a clocked digital subsystem. It provides sampling and synchronization of the input signal through two levels of clocked latches which, in turn, align the input signal with the digital subsystem clocks and resolve any potential metastable latch states that may occur during the synchronizing process. A feature of this design is additional, parallel logic that provides noise rejection capabilities to the synchronizing circuit. Many logic designs require an asynchronous input signal to be synchronized to a locally clocked logic subsystem, accompanied with a requirement to remove noise from the input prior to sampling the input signal. Asynchronous inputs are frequently generated by electronic components at some distance from the receiving logic. The separation of the components and the need to transmit signals between them creates a susceptibility to injected noise during the transmission process. Elaborate driver, receiver, and cabling configurations may be used to reduce this exposure. The digital filter feature of the present design can enhance or replace such configurations. The logic used to implement the noise rejection function operates in parallel with the synchronization function. Therefore, the digital filtering can be accomplished without introducing additional delay in processing the input signal. The figure shows the interface design. Two D-latches, FF1 and FF2, are connected in series and clocked with a local clock or oscillator to form a standard dual-rank synchronizing circuit. The asynchronous input signal is coupled to the data input of the first latch, FF1. If the clock signal to the latch and the data input change at approximately the same time, the input timing constraints of the latch may be violated and the output may be indeterminate for a period of time, i.e., the latch may become metastable. The clock period in this design is selected to be greater than the length of time required by the first latch to return to a known value (the resolution time of the latch). Therefore, the first latch will stabilize before the next clock signal is received by the second latch. This precludes any indeterminate state of the first latch from propagating to the output of the second latch. A significant disadvantage of typical dual-rank synchronizing designs is the sensitivity of the configuration to input noise on the data signal. If there is a noise pulse on the data input at the time the first latch is clocked, the noise pulse may be captured by the latch...