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Variable Duration Microprocessor Clock Generation

IP.com Disclosure Number: IPCOM000034923D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 7 page(s) / 118K

Publishing Venue

IBM

Related People

Fischer, LL: AUTHOR [+3]

Abstract

This article describes a microprocessor clock generator to interface with memory or peripheral devices having different or variable length access times without the loss in processor performance associated with prior-art approaches. (Image Omitted) Conventional approaches to such interface problems typically require either the insertion of microprocessor wait states, which are some multiple of the microprocessor clock, or the reduction of the microprocessor clock frequency to match the slowest attached component. Instead of adding clock cycles or lowering the clock frequency, this design allows the duration of each clock pulse to be dynamically varied to fit the component accessed. This matches the microprocessor and each attached component with a minimal loss in performance.

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Variable Duration Microprocessor Clock Generation

This article describes a microprocessor clock generator to interface with memory or peripheral devices having different or variable length access times without the loss in processor performance associated with prior-art approaches.

(Image Omitted)

Conventional approaches to such interface problems typically require either the insertion of microprocessor wait states, which are some multiple of the microprocessor clock, or the reduction of the microprocessor clock frequency to match the slowest attached component. Instead of adding clock cycles or lowering the clock frequency, this design allows the duration of each clock pulse to be dynamically varied to fit the component accessed. This matches the microprocessor and each attached component with a minimal loss in performance.

(Image Omitted)

Typical microprocessors are FET devices with clock frequencies in the 6 to 12 MHz range. By contrast, bipolar logic devices are available with operating frequencies in the 64 to 128 MHz range. This generator makes use of a high performance timing ring of bipolar logic components to develop the lower frequency clock signals required by the microprocessor. The high speed of the bipolar logic devices allows modifications to the microprocessor timings to be made in terms of multiples of the high frequency logic ring oscillator instead of the low frequency processor clock. In particular, the logic design used allows the clock cycle of the microprocessor to be extended by one or more periods of the lower frequency microprocessor clock. For the illustrative implementation to be described, the microprocessor clock period is 220 ns (approximately 4.5 MHz) and the high speed logic ring oscillator frequency is 32 MHz (approximately 31 ns). Thus, the present design allows modification to be made to the microprocessor timings with seven times the precision typically available. The modifications are made dynamically as required for each microprocessor cycle by extending the pulse width or duration of the microprocessor clock. The clock pulse is extended only by the minimum number of high speed oscillator periods required to match the particular memory or device accessed. For example, if an access is made to a memory device with a cycle time of 250 ns, one additional oscillator period might be added to the 220 ns microprocessor clock period instead of an entire clock cycle. The resulting microprocessor cycle would then be 250 ns instead of 438 ns. This represents the best-case saving for specific oscillator and clock frequencies used as an example. The actual savings depend on the access times and frequencies of access of the memory and device adapters used in any particular configuration. A feature of the present design is the ability to hold the microprocessor clocks in a particular state, freezing the microprocessor bus. This facility allows other microprocessors or DMA type devices to access the memory and...