Browse Prior Art Database

Pipeline Memory System for Drams

IP.com Disclosure Number: IPCOM000034926D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 93K

Publishing Venue

IBM

Related People

O'Neil, EF: AUTHOR

Abstract

A pipeline system is shown which minimizes the precharge time taken to accommodate re-write, restore, and refresh in a dynamic random-access memory (DRAM), such that the cycle time can be less than the access time. (Image Omitted) As DRAM density increases with each new generation, the die size increases, feature geometries decrease, and faster access times are featured. With increasing density/performance requirements, arrays are broken into smaller sub-arrays to maximize efficiency; however, device channel length scaling does not provide for sufficient access and cycle improvements. A method is shown for a pipelined memory systems where the cycle time can be less than the access time. In conventional DRAM operation, word and bit addresses are timed via a set of control signals, i.e.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Pipeline Memory System for Drams

A pipeline system is shown which minimizes the precharge time taken to accommodate re-write, restore, and refresh in a dynamic random-access memory (DRAM), such that the cycle time can be less than the access time.

(Image Omitted)

As DRAM density increases with each new generation, the die size increases, feature geometries decrease, and faster access times are featured. With increasing density/performance requirements, arrays are broken into smaller sub-arrays to maximize efficiency; however, device channel length scaling does not provide for sufficient access and cycle improvements. A method is shown for a pipelined memory systems where the cycle time can be less than the access time. In conventional DRAM operation, word and bit addresses are timed via a set of control signals, i.e., row address select (RAS) and column address select (CAS). This allows for multiplexing of the addresses and with additional CAS control, PAGE, SCM and TOGGLE functions may be provided. Broadside addressing and control, i.e., chip access with a chip select pulses, allows greater utilization of the entire array for speed/partitioning. The timing relationship shown in Fig. 1 shows that RAS control can sample RAS addresses in a pipeline fashion without triggering memory array restore with each rising edge of RAS. Therefore, once the RAS address address buffer is loaded, each CAS signal will send data streaming out of many word addresses in many different sub-arrays. Paging and SCM may also be performed since inboard sense amplifiers allow these functions an...