Browse Prior Art Database

On Chip LSSD Clock Generator With Zero Gap Between Master to Slave Clocks

IP.com Disclosure Number: IPCOM000034929D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Mueller, KD: AUTHOR [+2]

Abstract

The objective is to provide LSSD (level-sensitive scan design) clocks without any timing degradation with the design of a dedicated clock driver book that can be integrated within the register layout. The proposed solution allows: 1. An improvement of the chip performance up to 30% compared to the usual approach where the clock generation of a complete card is centralized in a dedicated 'Clock Chip' and then distributed to each latch. This improvement is achieved by the suppression of all timing skews that the usual approach induced both on the card clock distribution and on the 'on-chip' clock distribution before the clock signals are reaching the latch inputs. 2. An unique implementation applicable to any LSSD master/slave design. 3.

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On Chip LSSD Clock Generator With Zero Gap Between Master to Slave Clocks

The objective is to provide LSSD (level-sensitive scan design) clocks without any timing degradation with the design of a dedicated clock driver book that can be integrated within the register layout.

The proposed solution allows: 1. An improvement of the chip performance up to 30% compared to the usual approach where the clock generation of a complete card is centralized in a dedicated 'Clock Chip' and then distributed to each latch. This improvement is achieved by the suppression of all timing skews that the usual approach induced both on the card clock distribution and on the 'on-chip' clock distribution before the clock signals are reaching the latch inputs. 2. An unique implementation applicable to any LSSD master/slave design. 3. In test mode to use the normal A B and C LSSD clocks to the chip with their timing controlled by the tester. Each latch (or group of latches in the case of the same clocking requirements) includes in its layout an 'integrated' clock driver logic. This allows minimizing the wiring capacitances between the clock driver and the latch logic itself. This 'integrated' clock driver has 3 input signals (C, B, T) and 2 output signals (C*, B*).

Signal definitions: INPUTS - DESCRIPTION: C is the signal that will be propagated through the clock driver and used as the clock for the master latch. It can be generated with an external oscillator and then distributed to each clock driver. B is the signal that will be propagated through the clock driver and used as clock for the slave latch in TEST MODE. In SY...