Browse Prior Art Database

Versatile Row Redundancy Scheme for High Performance Random Access Memories

IP.com Disclosure Number: IPCOM000034935D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Morrish, JR: AUTHOR [+2]

Abstract

A method is shown for utilizing redundant rows in any of several different array blocks of a semiconductor memory as replacements for defective row, allowing more flexibility and productivity. This row redundancy implementation scheme affords the performance gained by using a replacement row from an adjacent array and also limits the number of selected arrays to conserve chip power. Versatility is built into the implementation by increasing the number of available replacement rows for each array section without increasing the total number of redundant rows on a chip. Referring to the figure, each memory array includes two redundant rows and a redundant row decoder (RD) per block. Also, each array has a separate clock to control array functions, i.e., set, restore, precharge, etc.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Versatile Row Redundancy Scheme for High Performance Random Access Memories

A method is shown for utilizing redundant rows in any of several different array blocks of a semiconductor memory as replacements for defective row, allowing more flexibility and productivity. This row redundancy implementation scheme affords the performance gained by using a replacement row from an adjacent array and also limits the number of selected arrays to conserve chip power. Versatility is built into the implementation by increasing the number of available replacement rows for each array section without increasing the total number of redundant rows on a chip. Referring to the figure, each memory array includes two redundant rows and a redundant row decoder (RD) per block. Also, each array has a separate clock to control array functions, i.e., set, restore, precharge, etc. and responds to an array block address if no redundant line is active. The clocks are enabled/disabled as a function of redundant row selection and only one array is activated at a time to conserve power. A redundant row is enabled when programmed to replace a defective regular row in any array block except the one in which the defective row is located. This versatility allows a redundant row in three of the four arrays shown to replace a defective regular row. All four arrays communicate with the same data in and data out (DI/DO) circuits (single bit, pairs, quads, etc.) so that a replacement row connects up wit...