Browse Prior Art Database

Link Bandwith Control Using a Hardware Pacing Mechanism

IP.com Disclosure Number: IPCOM000034937D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 51K

Publishing Venue

IBM

Related People

Costes, M: AUTHOR [+3]

Abstract

Different circumstances may require a bandwith limitation on a data transmission link. Furthermore, the bandwith limitation may well be voluntary in order to avoid end equipment monopolization. On the other hand, Response Time is an important characteristic of the link (high speed link) that needs to be preserved for a certain type of traffic, for example, interactive traffic. The pacing mechanism described hereunder provides pacing at the physical layer, implemented on the transmit side. This hardware pacing mechanism is based on the concept of average link use over a certain time interval, under control of the transmitter side. When link use remains under a defined limit, Response Time is preserved (full instantaneous bandwith).

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Link Bandwith Control Using a Hardware Pacing Mechanism

Different circumstances may require a bandwith limitation on a data transmission link. Furthermore, the bandwith limitation may well be voluntary in order to avoid end equipment monopolization. On the other hand, Response Time is an important characteristic of the link (high speed link) that needs to be preserved for a certain type of traffic, for example, interactive traffic. The pacing mechanism described hereunder provides pacing at the physical layer, implemented on the transmit side. This hardware pacing mechanism is based on the concept of average link use over a certain time interval, under control of the transmitter side. When link use remains under a defined limit, Response Time is preserved (full instantaneous bandwith). Should traffic increase, the pacing mechanism would force link utilization down to the desired value, hence avoiding overloading end equipment. The basic principle is to force the link to be idle for a desired percentage of time. The mechanism takes advantage of packet-mode operation over the link by controlling frame transmission. When frame transmission is held, continuous flags are transmitted. As shown in the figure, the pacing mechanism is controlled by four counters and a status latch (not shown): - C1 is the time counter. - C2 controls the number of effective bits being sent over the

link (not including flags). - C3 counts the number of frames (e.g., SDLC/HDLC) sent. - C4 is the auxiliary time counter (bit overflow counter; limited to Maxlength defined hereunder).

- Status latch is used to memorize the information that a

frame is currently being transmitted. It is set to Status = 'ON'

at the beginning of the transmission of a frame and reset to

Status = 'OFF' at the end of the transmission (ending flag

sent). For a given system, the following information is available: - Maxlength is the maximum length of the frames (not including flags). In all systems the length of the frame is bounded for

practical reasons. Maximum length is set to the upper bound

value. - Speed is the data rate over the link. - Mod is the maximum modulo count (8/128 : SDLC/HDLC). It may also be desirable to limit the number of frames transmitted in the time interval T regardless of the bit count (on top of SDLC modulo). Assume 'N' is the maximum number of frames to be transmitted in the time interval
T. Pacing Mechanism At initial time the counters are set to the following values: - C1 = T (has to be more than the time needed to transmit a frame of maximum length over the link.) - C2 = MAX (desired maximum number of effective bit...