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High Performance, Low Power Consumption NMOS P-Well on Chip Charge Pump

IP.com Disclosure Number: IPCOM000034942D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Hiltebeitel, NR: AUTHOR

Abstract

A circuit is shown which can yield more substrate bias and/or source higher leakage current with negligible impact to power consumption. By adding a depletion device to charge a node fully to Vdd, a NMOS P-well on chip substrate generator circuit can realize an improved substrate voltage (more negative) with negligible impact on power consumption. A basic charge pump circuit is shown in Fig. 1. Since T1 is a low voltage threshold (VT) device whose gate reaches Vdd, node N19 only charges to Vdd - low VT . This limits the coupling of node N21 to Vdd - low VT (C1/CN21). By charging C1 to Vdd, the down coupling of N21 and charge transfer through T6 can be increased. By making T1 smaller and adding a small depletion device T/A shown in Fig. 2, the charging of node N19 is shared between T1 and TA.

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High Performance, Low Power Consumption NMOS P-Well on Chip Charge Pump

A circuit is shown which can yield more substrate bias and/or source higher leakage current with negligible impact to power consumption. By adding a depletion device to charge a node fully to Vdd, a NMOS P-well on chip substrate generator circuit can realize an improved substrate voltage (more negative) with negligible impact on power consumption. A basic charge pump circuit is shown in Fig. 1. Since T1 is a low voltage threshold (VT) device whose gate reaches Vdd, node N19 only charges to Vdd - low VT . This limits the coupling of node N21 to Vdd - low VT (C1/CN21). By charging C1 to Vdd, the down coupling of N21 and charge transfer through T6 can be increased. By making T1 smaller and adding a small depletion device T/A shown in Fig. 2, the charging of node N19 is shared between T1 and TA. Most of the charge is done by T1 which is driven by node N18, and TA serves to top off the charge as node N20 rises. Now the coupling of N21 is increased to Vdd (C1/CN21). N20 also turns on T5 to bring N21 to ground and N18 falls while node N1 rises. T2 discharges N19 to ground and N21 is coupled to -Vdd (C1/CN21). Also, N20 is coupled down to -Vdd through T4 which turns off T/A. This prevent a DC current from flowing through T/A and T2 and impacting power consumption. With N21 coupling down further, T6 transfers more charge from the substrate and/or holds the substrate at a lower level than was possible...