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Word Line Redundancy With Improved Circuit and Wiring Density

IP.com Disclosure Number: IPCOM000034944D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Ellis, WF: AUTHOR [+2]

Abstract

A method is shown which will reduce circuit and wiring requirements when addressing redundant words in a memory array by multiplexing NOR nodes instead of true/complement (T/C) address buses, thereby saving chip real estate. To implement a redundant word scheme in a memory array, the defective address/addresses must be stored. One method is to use a fuse programmable read only memory (ROM) since it is not possible to predict which word line addresses will be defective. To allow for the possibility of replacing any defective word with a redundant word, the true and complement of all word line addresses must be made available. Further, the T/C address buses are multiplexed and latched (M/L) at word decode time, i.e.

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Word Line Redundancy With Improved Circuit and Wiring Density

A method is shown which will reduce circuit and wiring requirements when addressing redundant words in a memory array by multiplexing NOR nodes instead of true/complement (T/C) address buses, thereby saving chip real estate. To implement a redundant word scheme in a memory array, the defective address/addresses must be stored. One method is to use a fuse programmable read only memory (ROM) since it is not possible to predict which word line addresses will be defective. To allow for the possibility of replacing any defective word with a redundant word, the true and complement of all word line addresses must be made available. Further, the T/C address buses are multiplexed and latched (M/L) at word decode time, i.e., latched between row address scan (RAS) and column address scan (CAS) time, because the same buses are used for both word and bit addressing. With this scheme in place, a separate wiring channel is needed for addressing the word redundancy decoders and another address wiring channel is needed for the rest of the chip. Referring to the figure, array 10 is divided into quadrants 11, 12, 13 and 14 and each quadrant has four redundant word locations A, B, C and D. T/C address buses 15 interface with the redundant word address decoders 16. Since all that is needed to select or de- select word redundancy locations is the redundant word decoder NOR nodes 1, 2, 3 and 4, these nodes are multiplexed an...