Browse Prior Art Database

Memory Architecture With Flexibility in Bit-Wide Outputs

IP.com Disclosure Number: IPCOM000034947D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Miller, CP: AUTHOR [+2]

Abstract

A memory architecture is shown which can operate with single or multiple bit outputs by transforming the internal architecture. By providing a single memory chip with multiple modes of operation, a wide range of bit-wide customization can be satisfied with a single design and also simplify demands made upon manufacturing. A memory architecture is shown which can be modified by program control to provide the most common modes of operation, i.e., X1, X2, X4, X8,...etc. without the use of data gates. A memory architecture with X1 and X4 options is shown as an example in the figure. Note that each memory array I/O port, I/O 1, I/O 2,.... ..etc., has its own data latch 10 and control circuitry 11.

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Memory Architecture With Flexibility in Bit-Wide Outputs

A memory architecture is shown which can operate with single or multiple bit outputs by transforming the internal architecture. By providing a single memory chip with multiple modes of operation, a wide range of bit-wide customization can be satisfied with a single design and also simplify demands made upon manufacturing. A memory architecture is shown which can be modified by program control to provide the most common modes of operation, i.e., X1, X2, X4, X8,...etc. without the use of data gates. A memory architecture with X1 and X4 options is shown as an example in the figure. Note that each memory array I/O port, I/O 1, I/O 2,.... ..etc., has its own data latch 10 and control circuitry 11.
The I/O's are connected together by block/select pass devices 12 which are turned on for the X1 mode and off for the X4 mode by X1 control lines on the pass device gates. The X1 control lines allow the I/O's to operate independently or together. The multiplexer circuit 13 selects the memory row (A, B, C or D) to be utilized as output. When the architecture is in the lower mode of operation,
i.e., X1 in the example, all unused circuitry is put in a tri-state mode by X1 control lines to prevent interference from these circuits at the lower modes of operation.

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