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Configurable 2**n Power Incrementer

IP.com Disclosure Number: IPCOM000034953D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Levy, JR: AUTHOR [+2]

Abstract

Carry break circuits are shown for a binary incrementer which, when inserted at specific locations in a carry path, can be utilized to increment a binary value of any length by any power of two. By configuring incrementers utilizing custom bit slices with carry break circuits between the odd and even bit position, incrementers of variable length and capability can be structured. One custom bit slice contains an odd and even bit position with a carry break circuit between the two composed of a NAND circuit and two inverters which steer the carries when incrementing by 2N (where N is odd), i.e., 21, 23, 25,... etc.

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Configurable 2**n Power Incrementer

Carry break circuits are shown for a binary incrementer which, when inserted at specific locations in a carry path, can be utilized to increment a binary value of any length by any power of two. By configuring incrementers utilizing custom bit slices with carry break circuits between the odd and even bit position, incrementers of variable length and capability can be structured. One custom bit slice contains an odd and even bit position with a carry break circuit between the two composed of a NAND circuit and two inverters which steer the carries when incrementing by 2N (where N is odd), i.e., 21, 23, 25,... etc. Another custom bit slice contains an odd and even bit position with a carry break circuit between the two composed of a 2-WAY passgate multiplexer circuit which steers the carries when incrementing by 2N (where N is even), i.e., 22, 24, 26, etc. The two bit custom slice used for a carry steering circuit when incrementing by 2N (where N is odd) is shown in Fig. 1. When a negative control signal is applied to the input of inverter 10 (Increment by 2N, where N = odd) node A goes negative. Node B is forced negative by the input control line (Increment by 2N, where N = even) causing the NAND output at node C to go negative and be inverted by inverter
11. This circuit blocks the normal carry propagated from the adjacent lower order bit position when incrementing by any odd power of two. A two-way passgate multiplexer, shown in Fig. 2, is also used as a steerage mechanism in a binary incrementer. Because a pass transistor is a bilatera...