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Improved Mcleod Loops for MOS Testing

IP.com Disclosure Number: IPCOM000034960D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 51K

Publishing Venue

IBM

Related People

Turner, ME: AUTHOR

Abstract

An extension of the McLeod Loop Methodology is disclosed which uses a dominant set-reset latch, such as the critical gating function, rather than an OR gate as in the prior art, to facilitate independent characterization of rising and falling delays of inverting logic functions. McLeod loops are modified ring oscillators used to extract logic gate rise and fall delays to characterize many bipolar technologies. Positive logic (AND, OR) is readily available in bipolar technologies; however, there are no positive logic primitives available in MOS technologies. A solution is shown for characterizing strictly negative logic (NAND, NOR) of MOS technologies using McLeod loops to obtain separate rise and fall delays. Fig. 1 shows the basic circuit configuration of the McLeod loops.

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Improved Mcleod Loops for MOS Testing

An extension of the McLeod Loop Methodology is disclosed which uses a dominant set-reset latch, such as the critical gating function, rather than an OR gate as in the prior art, to facilitate independent characterization of rising and falling delays of inverting logic functions. McLeod loops are modified ring oscillators used to extract logic gate rise and fall delays to characterize many bipolar technologies. Positive logic (AND, OR) is readily available in bipolar technologies; however, there are no positive logic primitives available in MOS technologies. A solution is shown for characterizing strictly negative logic (NAND, NOR) of MOS technologies using McLeod loops to obtain separate rise and fall delays. Fig. 1 shows the basic circuit configuration of the McLeod loops. Input X and Y are DC gates used to set-up and control rise/fall measurements. The first frequency measurement is taken by setting X low and Y high. The period of measurement is dependent on Path 1 as shown by the following turn-on and turn-off times: P1 = Af + Br + Cr + Er + Ar + Bf + Cf + Ef where f = fall time and r = rise time. Similarly, by setting X high and Y low, a second frequency measurement is made that is dependent upon Path 2, as shown by the following: P2 = Af + Fr + Gr + Dr + Er + Ar + Ff + Gf + Df +

Ef The final measurement is taken by setting both X and Y low. The period is now dependent upon both Path 1 and Path 2 as shown by the following: P3 = Af + Br + Cr + Er + Ar + Ff + Gf + Df + Ef The key to this measurement is the designed-in race condition and the characteristics of circuit E. The inputs to both Path 1 and Path 2 are always the same and the outputs match except for the longer delay through Path 2 caused by the extra logic stage delay. The characteristics of E are that it will respond to the first of two rising inputs and the second of two falling inputs as shown in Fig. 2a. A two way logical OR performs this function. In this configuration, when C and D are turning on, E will respond to C which is turning on first. Conversely, when D and C are turning off, E will respond to D which is turning off last. This explains the P3 measurement that is dependent on the turn-on delay through C and the turn-off delay through D. This assumes the same number of inverters on each path, i.e., block D is non-inverting. To obtain the falling delay difference caused by the extra logic stage, P1 is subtracted from P3 as follows: P3 = Af + Br + Cr + Er + Ar + Ff + Gf + Ef + Df P1 = Af + Br + Cr + Er + Ar + Bf + Cf + Ef P3-P1 = (Ff - Bf) + (GF - Cf) + Df Circuits F and B are designed to be the same with equal loading and delays which cancel out. Similarly, Gf and Cf also cancel if their delays and loads are equal. P3-P1 is the delay added by the falling delay of the extra logic stage. Similarly, the rise time delay can be obtained by subtracting P3 from P2; therefore, P2-P3 = (Fr - Br) + (Gr - Cr) + Dr The B and F

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