Browse Prior Art Database

Two Mask Process for Making Borderless Openings to Three Different Levels Within a Microcircuit

IP.com Disclosure Number: IPCOM000034963D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Koburger, CW: AUTHOR [+2]

Abstract

A two mask process is described to create openings through a planarized insulator (1) to a non-planar region for deposition of a conductive strap, (2) to a diffusion for a contact opening, and (3) to a polysilicon conductive line. The masks are designed to be "borderless", i.e., without sacrificing density, they are designed to prevent hole overlap onto adjacent polysilicon wiring when normal misalignment occurs. Referring to Fig. 1, a trench in silicon substrate 4 has thin insulation 2a on its sidewalls and is filled with conductive polysilicon 2b. Conductive polysilicon lines 6 and 8 are formed on gate insulation 10. Thin sidewall insulation 12 is grown on the lines 6 and 8 after line etching and thick top surface insulating film 14 is deposited before line etching.

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Two Mask Process for Making Borderless Openings to Three Different Levels Within a Microcircuit

A two mask process is described to create openings through a planarized insulator (1) to a non-planar region for deposition of a conductive strap, (2) to a diffusion for a contact opening, and (3) to a polysilicon conductive line. The masks are designed to be "borderless", i.e., without sacrificing density, they are designed to prevent hole overlap onto adjacent polysilicon wiring when normal misalignment occurs. Referring to Fig. 1, a trench in silicon substrate 4 has thin insulation 2a on its sidewalls and is filled with conductive polysilicon 2b. Conductive polysilicon lines 6 and 8 are formed on gate insulation 10. Thin sidewall insulation 12 is grown on the lines 6 and 8 after line etching and thick top surface insulating film 14 is deposited before line etching. Source and drain diffusions 16 and 18 are created in substrate silicon 4 and the entire surface is coated with etch stop layer 20. A first contact hole mask is used to create photoresist pattern 22 on the surface of planarized glass insulator 24. Note that hole openings in photoresist 22 are shown misaligned to the left with respect to polysilicon lines 6 and 8. The cross-section shown in Fig. 2 is achieved as follows. Reactive ion etching (RIE) is used to etch completely through glass 24 beneath hole openings in photoresist 22. The etch stop material 20 is completely inert in the RIE environment for etching glass 24. Thus, glass 24 may be completely removed in the region above trench 2 wh...