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IOP/IOA Bus Isolation for Basic Assurance Tests

IP.com Disclosure Number: IPCOM000034972D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 66K

Publishing Venue

IBM

Related People

Bilder, MM: AUTHOR [+3]

Abstract

This article describes a technique for isolation of failures on the input output processor (IOP)/input output adapter (IOA) bus during power up. In a data processor system where there is no IOP/IOA bus isolation for failures on the bus during power up, the whole subsystem is suspect. Fig. 1 shows the IOP/IOA hardware in blocks diagram. The incorporation of an isolation algorithm at power up time will isolate a failing field replaceable unit (FRU) due to IOA bus problems. To limit exposure the IOAs are all degated, then their basic assurance tests (BATs) are run one at a time so that any bus failure will be isolated to the IOP/IOA FRU running at that time. When all the IOAs have completed, then a test of the number of IOA failures will isolate to an IOP or an IOA. Fig. 2 is a flow chart of the technique utilized.

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IOP/IOA Bus Isolation for Basic Assurance Tests

This article describes a technique for isolation of failures on the input output processor (IOP)/input output adapter (IOA) bus during power up. In a data processor system where there is no IOP/IOA bus isolation for failures on the bus during power up, the whole subsystem is suspect. Fig. 1 shows the IOP/IOA hardware in blocks diagram. The incorporation of an isolation algorithm at power up time will isolate a failing field replaceable unit (FRU) due to IOA bus problems. To limit exposure the IOAs are all degated, then their basic assurance tests (BATs) are run one at a time so that any bus failure will be isolated to the IOP/IOA FRU running at that time. When all the IOAs have completed, then a test of the number of IOA failures will isolate to an IOP or an IOA. Fig. 2 is a flow chart of the technique utilized.

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