Browse Prior Art Database

Simplified Asynchronous Communications Interface Network

IP.com Disclosure Number: IPCOM000034973D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 4 page(s) / 70K

Publishing Venue

IBM

Related People

Rudquist, ML: AUTHOR [+3]

Abstract

A peripheral processor may use the simplified asynchronous communication network for message transfer operation with a processor unit 10 (see Fig. 1) having a bus-oriented system. This bus-oriented system requires a unique interface to interface the processor unit's parallel data bus to the peripheral's serial asynchronous data communication channel. If the processor unit has other dedicated functions; then the interface must provide transmit and receive control as well as data formatting and buffering. This network uses minimal circuit hardware that provides efficient execution of processor code. (Image Omitted) A serial asynchronous communication channel (see Fig.

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Simplified Asynchronous Communications Interface Network

A peripheral processor may use the simplified asynchronous communication network for message transfer operation with a processor unit 10 (see Fig. 1) having a bus-oriented system. This bus-oriented system requires a unique interface to interface the processor unit's parallel data bus to the peripheral's serial asynchronous data communication channel. If the processor unit has other dedicated functions; then the interface must provide transmit and receive control as well as data formatting and buffering. This network uses minimal circuit hardware that provides efficient execution of processor code.

(Image Omitted)

A serial asynchronous communication channel (see Fig. 1) that links a peripheral processor 12 with a bus-oriented processor unit 10, for example, requires interface logic 14 that relieves the processor unit from transmit and receive control tasks as well as data formatting and buffering. The communication channel, shown in Fig. 1, is half duplexed and consists of four signal lines: two serial data lines (transmit and receive), and two handshaking control signals. The handshaking signals are used for both inhibiting simultaneous message transfers and for acknowledging the successful receipt of a message transfer. This additionally requires the communication interface 14 to arbitrate control of the communication channel. Peripheral 12 activates "Handshake 1" to indicate a message transfer request and keeps this line active until the completion of the message transfer. Similarly, "Handshake 2" is activated to inform peripheral 12 of a message transfer request and remains active until the completion of the message transfer. Peripheral 12 waits a small amount of time after activating "Handshake 1" and grants the message transfer from processor unit 10. Each device acknowledges the receipt of a successful message transfer by generating a pulse on its respective handshaking signal. The network shown in Fig. 2 can be used as the simple asynchronous communications interface 14. The major components consist of selection and control logic 16, data buffer 18 to stack the message, serial data shift register (SDSR) 20 for transmitting and receiving serial data, a baud rate generator 22, status register 24, and timeout counter 26. Selection and control hardware is used to indicate whether the interface is idle, in a transmit mode, or in a receive mode. Since data is transferred in only one direction at a time, a single data buffer can be used. The data buffer is addressable to the processor unit. For transmitting data to peripheral 12 a packet of data from data buffer 18 is copied into the SDSR 20. Baud rate generator 22 is enabled, and data is transmitted serially across the communication channel of Fig. 1 to peripheral 12. After the packet of data is transferred, baud rate generator 22 is disabled. For receiving data from peripheral 12, baud rate generator 22 is enabled for each...