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# Pseudo Nibble Parity for Fast Shifter Parity Predict

IP.com Disclosure Number: IPCOM000034985D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 4 page(s) / 102K

IBM

## Related People

Freerksen, DL: AUTHOR [+2]

## Abstract

Maintaining byte parity is a common method of error checking for multi- byte registers. When registers such as these are used as inputs for arithmetic, prediction of the output parity bits can be made using an input data register and input parity. In floating point arithmetic hardware, a common arithmetic operation is to shift the fraction to the left or to the right. The shift amount might be as few as zero, or as many as 56 for a double precision number. The most common method of performing a fraction shift is to break the shift down into three steps - a rough shift, a medium shift, and a (Image Omitted) fine shift. - The rough shift performs a shift of 0, 16, 32 or 48. - The medium shift performs a shift of 0, 4, 8 or 12. - The fine shift performs a shift of 0, 1, 2 or 3.

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Pseudo Nibble Parity for Fast Shifter Parity Predict

Maintaining byte parity is a common method of error checking for multi- byte registers. When registers such as these are used as inputs for arithmetic, prediction of the output parity bits can be made using an input data register and input parity. In floating point arithmetic hardware, a common arithmetic operation is to shift the fraction to the left or to the right. The shift amount might be as few as zero, or as many as 56 for a double precision number. The most common method of performing a fraction shift is to break the shift down into three steps - a rough shift, a medium shift, and a

(Image Omitted)

fine shift. - The rough shift performs a shift of 0, 16, 32 or 48. - The medium shift performs a shift of 0, 4, 8 or 12. - The fine shift performs a shift of 0, 1, 2 or
3. With these three steps all possible shifts between 0 and 63 inclusive can be obtained. The following method is a fast method of parity predict for the medium shifts (0,4,8,12 bits) for large arithmetic shifters. Predicting parity for the rough shift is done simply by shifting the parity bits with their corresponding data bytes. This can be done because the shift amount is always a multiple of 8 bits (one byte). Predicting parity for the medium shift is more difficult. If the medium shift is 0 or 8, then the parity bit can be shifted as in the rough shift parity predict. However, if the medium shift amount is 4 or 12, then four bits are being shifted out of a particular parity field, and four new bits are being shifted into that same field. A new

(Image Omitted)

parity change equation must be generated to be XORed with the old parity bit for that field. That parity change equation exists in two parts. The first part is the XOR of all bits that were shifted out of that field to "undo" their effect on the parity. The second part consists of an XOR of all the bits that were shifted into that field to "add in" their effect on the parity. This method of parity predict for medium shifts is too slow to implement on certain floating point processor. Traditionally, XORs are very time-consuming levels of logic. AND gates and OR gates are much quicker in terms of delay, so they should be used wherever possible on critical delay paths. Fig. 1 shows the shifter structure if byte parity is used, and maintained through each level of the shifter. Notice the stages of data XOR between the Rough parity and Medium parity stages, and also between the Medium parity and Fine parity stages. Fig. 2 shows the data XORs being generated from the Rough shift

(Image Omitted)

output to...