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Cell-Efficient LSSD Asynchronous Edge-Triggered Data Latch and Recognizer

IP.com Disclosure Number: IPCOM000034994D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 77K

Publishing Venue

IBM

Related People

Abler, JM: AUTHOR [+3]

Abstract

A common problem in any LSSD design is to synchronize external asynchronous signals to the internal clocks. This article describes a method of latching external data synchronously with the internal clocks, while complying with all LSSD testability rules. This clocking methodology allows an asynchronous signal to generate a clock to latch the data. The latching of the data is not dependent on the internal clocks of the chip (see Fig. 1). It should be stressed that this method of latching data is completely LSSD compatible. The Sample Pulse is used when operating the chip in normal mode; this represents the Asynchronous External Clock. The System 3 Clock is used by all of the Asynchronous Data Latches on the chip when generating LSSD test patterns. Asynchronous data is latched into Buffer 1 on the edge of Sample Pulse.

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Cell-Efficient LSSD Asynchronous Edge-Triggered Data Latch and Recognizer

A common problem in any LSSD design is to synchronize external asynchronous signals to the internal clocks. This article describes a method of latching external data synchronously with the internal clocks, while complying with all LSSD testability rules. This clocking methodology allows an asynchronous signal to generate a clock to latch the data. The latching of the data is not dependent on the internal clocks of the chip (see Fig. 1). It should be stressed that this method of latching data is completely LSSD compatible. The Sample Pulse is used when operating the chip in normal mode; this represents the Asynchronous External Clock. The System 3 Clock is used by all of the Asynchronous Data Latches on the chip when generating LSSD test patterns. Asynchronous data is latched into Buffer 1 on the edge of Sample Pulse. This data is synchronized to the internal clocks as it is loaded into the next Buffer (see Fig. 1). This eliminates metastability problems that may exist between the asynchronous sample pulses' latching of data, and the internal clocks that gate the data to the next Buffer. Once the data loaded into the next Buffer, Buffer 1 can be loaded with new data.

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Fig. 1 shows that the data hold time after the Sample Pulse transition approaches 0 nsec. This is dependent only on the gate delays of the circuits and the set-up time of the data latches. This makes the hold-tim...