Browse Prior Art Database

Silicide Interface Monitor

IP.com Disclosure Number: IPCOM000034995D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Nowak, EJ: AUTHOR

Abstract

A structure is disclosed for providing direct measurement of silicide-to-diffusion (n+ or p+) interface resistance. The series resistance of field-effect transistors (FETs) becomes increasingly important as device lengths are shortened. A significant component of the FET series resistance (RE) is contributed by the interface between the metal silicide, e.g., titanium silicide (TiSi2) and the source/drain silicon (n+/p+) in technologies with silicide source/drains. Current techniques allow a measurement of the total series resistance and are incapable of separating the interface component (RI) from the component due to the resistance of the doped silicon. This limitation imposes interpretation difficulties on experiments which change both components, e.g.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 62% of the total text.

Page 1 of 2

Silicide Interface Monitor

A structure is disclosed for providing direct measurement of silicide-to-diffusion (n+ or p+) interface resistance. The series resistance of field-effect transistors (FETs) becomes increasingly important as device lengths are shortened. A significant component of the FET series resistance (RE) is contributed by the interface between the metal silicide, e.g., titanium silicide (TiSi2) and the source/drain silicon (n+/p+) in technologies with silicide source/drains. Current techniques allow a measurement of the total series resistance and are incapable of separating the interface component (RI) from the component due to the resistance of the doped silicon. This limitation imposes interpretation difficulties on experiments which change both components, e.g., doping profile changes, and leads to ambiguity in setting the direction of process work required to improve this interface. A novel FET layout shown in Fig. 1 allows direct measurement of the interface resistance without ambiguity. Referring to Fig. 2, a structure similar to a FET is utilized, except that one terminal is pdoped and the other terminal is n+ doped. The p+ terminal is biased positive and the current path is vertical from the silicide to the p+, to the p-epi, to the p+ substrate where it is returned. The gate is biased above NFET VT (typically about +5 volts). The p+ is the most positive potential in the silicon and the n+ charges to a potential equal to that of the p+ jus...