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Streamline High-Speed Buffer Control Circuit for Minimal Latch Usage With LSSD Testability

IP.com Disclosure Number: IPCOM000034996D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Abler, JM: AUTHOR [+3]

Abstract

A buffer control circuit is implemented following LSSD design rules. A cell savings and cycle time reduction is accomplished by using both the latch 1 and latch 2 sections of each LSSD latch as separate latches. The amount of cell savings and cycle time reduction is dependent upon the size and depth of the buffer. Refer to the equations below to determine their benefit to a particular implementation. This design incorporates L2* latches, which allow the user to supply separate functional clocks to the different buffer stages. Using a 4-Deep, *-Wide buffer, the following example has been created, which can be seen in the figure above. The design is separated into two sections: 1. Control Section 2.

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Streamline High-Speed Buffer Control Circuit for Minimal Latch Usage With LSSD Testability

A buffer control circuit is implemented following LSSD design rules. A cell savings and cycle time reduction is accomplished by using both the latch 1 and latch 2 sections of each LSSD latch as separate latches. The amount of cell savings and cycle time reduction is dependent upon the size and depth of the buffer. Refer to the equations below to determine their benefit to a particular implementation. This design incorporates L2* latches, which allow the user to supply separate functional clocks to the different buffer stages. Using a 4-Deep, *-Wide buffer, the following example has been created, which can be seen in the figure above. The design is separated into two sections: 1. Control Section

2. Data Buffer Section Loading data into buffer (Buff) 1 during an S1 Clock (for L1 latch), also sets its corresponding control section identifying data being present. On the following S2 Clock (for the L2 latch), data immediately moves into the L2 latch, which is identified as Buff 2. The next S1 clock will move data into Buff 3, and finally Buff 4 on the next S2. As described with Buff 1, the corresponding control section keeps track of where the data is located, and whether new data can be latched in. Complete pulse, which is provided by the circuitry accepting data out of Buff 4, is used to clear the Buff 4 control logic. Note that S1 can be asynchronous data which, when loaded i...