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Test Logic for Timer Verification

IP.com Disclosure Number: IPCOM000034998D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Kuhlman, CL: AUTHOR

Abstract

This invention describes a method to test a 3-second timer efficiently during chip manufacture, and how to verify correct operation of the timer during the diagnostic checkout at system power on time without waiting the full 3 seconds. The description of the hardware to support the unique method of testing the timer is as follows. As shown in the figure, the test logic includes 1. Three microcode addressable bits for timer test mode, timer reset, and timer test OK, 2. Logic to break up the timer into 7-bit sections, and 3. Error-detection logic. The test mode bit A being set forces the 28-bit timer into 7-bit sections and also forces the carry-in to each section to be active. This causes all sections to count together.

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Test Logic for Timer Verification

This invention describes a method to test a 3-second timer efficiently during chip manufacture, and how to verify correct operation of the timer during the diagnostic checkout at system power on time without waiting the full 3 seconds. The description of the hardware to support the unique method of testing the timer is as follows. As shown in the figure, the test logic includes 1. Three microcode addressable bits for timer test

mode, timer reset, and timer test OK,

2. Logic to break up the timer into 7-bit sections,

and

3. Error-detection logic. The test mode bit A being set forces the 28-bit timer into 7-bit sections and also forces the carry-in to each section to be active. This causes all sections to count together. The test mode bit being reset forces the 7-bit sections to be one large timer. The timer reset bit B being set forces a reset to the all bits in the timer. The timer test OK bit D is reset when the timer test mode is set and stays inactive until the timer checks out to be working correctly, at which time this bit is set.

If the timer is found to be faulty, the timer test OK bit remains reset. The error detection logic involves doing an exclusive-OR of each of the carry-outs E with at least one of the other carry-outs, and also anding all of the carry-outs together. If the output of the exclusive-OR logic indicates a miscompare, then an error latch C is set, which would prevent the timer test OK bit from being set. The ANDing of all of the carry-outs F is used to set the...