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Browse Prior Art Database

Three-Dimensional Single-Crystal Dynamic Ram Cell

IP.com Disclosure Number: IPCOM000035002D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 63K

Publishing Venue

IBM

Related People

Lu, NC: AUTHOR [+2]

Abstract

This article describes a new three-dimensional DRAM cell which eliminates the oxide layer between the transistor body and polysilicon inside the trench and allows the source region having a good registration to the polysilicon inside the trench. The cell structure is shown in Fig. 1. The polysilicon surface is exposed and a N+P junction isolates the capacitor from the access transistor. The source region is connected to the polysilicon surface by a deep N+ region. The capacitance is obtained not only from the trench capacitor sidewalls but also from the N+P junction capacitance on top of the trench surface.

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Three-Dimensional Single-Crystal Dynamic Ram Cell

This article describes a new three-dimensional DRAM cell which eliminates the oxide layer between the transistor body and polysilicon inside the trench and allows the source region having a good registration to the polysilicon inside the trench. The cell structure is shown in Fig. 1. The polysilicon surface is exposed and a N+P junction isolates the capacitor from the access transistor. The source region is connected to the polysilicon surface by a deep N+ region. The capacitance is obtained not only from the trench capacitor sidewalls but also from the N+P junction capacitance on top of the trench surface.

(Image Omitted)

The fabrication procedures are described in the following process steps: Step (1) Assuming the silicon substrate having p- epitaxial layer on top of heavily p+ doped wafer (it can be just p+ wafer, depending on the thickness of the epi layer required), a thick oxide layer or a composite layer of Si3N4 and SiO2 is formed over the p- epi layer. After suitable lithography steps, this Si3N4/SiO2 layer is used as a mask to form a trench in silicon substrate by RIE (reactive ion etching). Step (2) After a thin oxide layer is thermally grown, a thin nitride layer is deposited and thermally densified in an oxide ambient to form a composite film of SiO2/Si3N4/SiO2 for the storage capacitor insulator. Then a thick polysilicon film is deposited to fill the trench and is heavily n+ doped. Step (3) The polysilicon film is etched by RIE or by grinding technique such that the surface of poly is lined up with the substrate surface. The nitride layer over the substrate surface is used for etch stop (Fig. 2). Step (4) The nitride/oxide layers over the substrate are removed by anisotropic etching. Then a large area of single crystal is exposed plus smaller areas of polysilicon inside the trenches. Step (5) Then a lightly doped p-type silicon layer is epitaxially grown. Since a large area of the single-crystal silicon substrate is exposed to the epitaxial growth and provides the required single- crystal epitaxy seeds, a single-crystalline silicon film can be obtained with g...